diff mbox series

[RFC,v2,19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper

Message ID 20200722091641.8834-20-frank.chang@sifive.com (mailing list archive)
State New, archived
Headers show
Series target/riscv: support vector extension v0.9 | expand

Commit Message

Frank Chang July 22, 2020, 9:15 a.m. UTC 
From: Frank Chang <frank.chang@sifive.com>

For floating-point operations, the scalar can be taken from a scalar
f register. If FLEN > SEW, the value in the f registers is checked for
a valid NaN-boxed value, in which case the least-significant SEW bits
of the f register are used, else the canonical NaN value is used.

Add helper to generate the correspond NaN-boxed value or the SEW-bit
canonical NaN for floating-point operations.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/helper.h        |  2 ++
 target/riscv/vector_helper.c | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

Comments

Richard Henderson July 22, 2020, 7:15 p.m. UTC | #1 
On 7/22/20 2:15 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
> 
> For floating-point operations, the scalar can be taken from a scalar
> f register. If FLEN > SEW, the value in the f registers is checked for
> a valid NaN-boxed value, in which case the least-significant SEW bits
> of the f register are used, else the canonical NaN value is used.
> 
> Add helper to generate the correspond NaN-boxed value or the SEW-bit
> canonical NaN for floating-point operations.
> 
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/helper.h        |  2 ++
>  target/riscv/vector_helper.c | 32 ++++++++++++++++++++++++++++++++
>  2 files changed, 34 insertions(+)

The helper can be done inline in two tcg ops.

Though, really, we need to coordinate with Liu Zhiwei's other patch set that
also deals with nan-boxing.


r~
Frank Chang July 23, 2020, 7:13 a.m. UTC | #2 
On Thu, Jul 23, 2020 at 3:15 AM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 7/22/20 2:15 AM, frank.chang@sifive.com wrote:
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > For floating-point operations, the scalar can be taken from a scalar
> > f register. If FLEN > SEW, the value in the f registers is checked for
> > a valid NaN-boxed value, in which case the least-significant SEW bits
> > of the f register are used, else the canonical NaN value is used.
> >
> > Add helper to generate the correspond NaN-boxed value or the SEW-bit
> > canonical NaN for floating-point operations.
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > ---
> >  target/riscv/helper.h        |  2 ++
> >  target/riscv/vector_helper.c | 32 ++++++++++++++++++++++++++++++++
> >  2 files changed, 34 insertions(+)
>
> The helper can be done inline in two tcg ops.
>
> Though, really, we need to coordinate with Liu Zhiwei's other patch set
> that
> also deals with nan-boxing.
>
>
So, it's better to leverage the codes at:
https://patchew.org/QEMU/20200626205917.4545-1-zhiwei_liu@c-sky.com/
but has to extend for the case of SEW=16?

Frank Chang


>
> r~
>
Richard Henderson July 23, 2020, 4:14 p.m. UTC | #3 
On 7/23/20 12:13 AM, Frank Chang wrote:
> On Thu, Jul 23, 2020 at 3:15 AM Richard Henderson <richard.henderson@linaro.org
> <mailto:richard.henderson@linaro.org>> wrote:
> 
>     On 7/22/20 2:15 AM, frank.chang@sifive.com <mailto:frank.chang@sifive.com>
>     wrote:
>     > From: Frank Chang <frank.chang@sifive.com <mailto:frank.chang@sifive.com>>
>     >
>     > For floating-point operations, the scalar can be taken from a scalar
>     > f register. If FLEN > SEW, the value in the f registers is checked for
>     > a valid NaN-boxed value, in which case the least-significant SEW bits
>     > of the f register are used, else the canonical NaN value is used.
>     >
>     > Add helper to generate the correspond NaN-boxed value or the SEW-bit
>     > canonical NaN for floating-point operations.
>     >
>     > Signed-off-by: Frank Chang <frank.chang@sifive.com
>     <mailto:frank.chang@sifive.com>>
>     > ---
>     >  target/riscv/helper.h        |  2 ++
>     >  target/riscv/vector_helper.c | 32 ++++++++++++++++++++++++++++++++
>     >  2 files changed, 34 insertions(+)
> 
>     The helper can be done inline in two tcg ops.
> 
>     Though, really, we need to coordinate with Liu Zhiwei's other patch set that
>     also deals with nan-boxing.
> 
> 
> So, it's better to leverage the codes
> at: https://patchew.org/QEMU/20200626205917.4545-1-zhiwei_liu@c-sky.com/
> but has to extend for the case of SEW=16? 

Yes, or what becomes of that patch set upon revision.


r~
diff mbox series

Patch

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index acc298219d..3cbd66a887 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1150,3 +1150,5 @@  DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_3(narrower_nanbox_fpr, i64, i64, i32, env)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 83e317c500..fb689ab3f9 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3207,6 +3207,38 @@  GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4, clearl)
 /*
  *** Vector Float Point Arithmetic Instructions
  */
+
+/*
+ * For SEW < FLEN,
+ * if f is not correctly NaN-boxed for SEW bits,
+ * canonical SEW-bit NaN is returned.
+ * Otherwise, original f is returned.
+ */
+static uint64_t narrower_nanbox_fpr(uint64_t f, uint32_t sew, float_status *s)
+{
+    uint64_t mask = MAKE_64BIT_MASK(sew, 64 - sew);
+    if ((f & mask) == mask) {
+        return f;
+    } else {
+        switch (sew) {
+        case 16:
+            return float16_default_nan(s);
+        case 32:
+            return float32_default_nan(s);
+        case 64:
+            return float64_default_nan(s);
+        default:
+            g_assert_not_reached();
+        }
+    }
+}
+
+uint64_t HELPER(narrower_nanbox_fpr)(uint64_t f, uint32_t sew,
+                                     CPURISCVState *env)
+{
+    return narrower_nanbox_fpr(f, sew, &env->fp_status);
+}
+
 /* Vector Single-Width Floating-Point Add/Subtract Instructions */
 #define OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)   \
 static void do_##NAME(void *vd, void *vs1, void *vs2, int i,   \