| Message ID | 20200803222656.63936-1-pcc@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/arm: Fix decode of {LD,ST}RA[AB] instructions | expand |
On Mon, Aug 3, 2020 at 3:27 PM Peter Collingbourne <pcc@google.com> wrote: > > These instructions use zero as the discriminator, not SP. Oh, there is no such thing as STRAA/STRAB. I must have been confused by the name of the function, disas_ldst_pac. I will send a v2 with a fixed commit message, and another patch to rename the function to disas_ld_pac. Peter > > Signed-off-by: Peter Collingbourne <pcc@google.com> > --- > target/arm/translate-a64.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 8c0764957c..c996ca1393 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -3429,9 +3429,11 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, > > if (s->pauth_active) { > if (use_key_a) { > - gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); > + gen_helper_autda(dirty_addr, cpu_env, dirty_addr, > + new_tmp_a64_zero(s)); > } else { > - gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); > + gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, > + new_tmp_a64_zero(s)); > } > } > > -- > 2.28.0.163.g6104cc2f0b6-goog >
On 8/3/20 5:21 PM, Peter Collingbourne wrote: > On Mon, Aug 3, 2020 at 3:27 PM Peter Collingbourne <pcc@google.com> wrote: >> >> These instructions use zero as the discriminator, not SP. > > Oh, there is no such thing as STRAA/STRAB. I must have been confused > by the name of the function, disas_ldst_pac. I will send a v2 with a > fixed commit message, and another patch to rename the function to > disas_ld_pac. It's called decode_ldst_pac because the Arm ARM section is called "Load/store register (pac)". Page C4-311 in the F.a revision. But yes, there are only loads defined in the section. r~
On Tue, Aug 4, 2020 at 8:41 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > On 8/3/20 5:21 PM, Peter Collingbourne wrote: > > On Mon, Aug 3, 2020 at 3:27 PM Peter Collingbourne <pcc@google.com> wrote: > >> > >> These instructions use zero as the discriminator, not SP. > > > > Oh, there is no such thing as STRAA/STRAB. I must have been confused > > by the name of the function, disas_ldst_pac. I will send a v2 with a > > fixed commit message, and another patch to rename the function to > > disas_ld_pac. > > It's called decode_ldst_pac because the Arm ARM section is called "Load/store > register (pac)". Page C4-311 in the F.a revision. > > But yes, there are only loads defined in the section. I see. Arguably the ARM ARM section is misnamed then. There is a sibling section named "Load register (literal)", so there is precedent for naming a section after the types of instructions that are actually supported. I will send mail to errata@arm.com to see if the section can be renamed. Peter
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8c0764957c..c996ca1393 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3429,9 +3429,11 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, if (s->pauth_active) { if (use_key_a) { - gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); + gen_helper_autda(dirty_addr, cpu_env, dirty_addr, + new_tmp_a64_zero(s)); } else { - gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); + gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, + new_tmp_a64_zero(s)); } }
These instructions use zero as the discriminator, not SP. Signed-off-by: Peter Collingbourne <pcc@google.com> --- target/arm/translate-a64.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)