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[RFC,v3,16/71] target/riscv: add fp16 nan-box check generator function

Message ID 20200806104709.13235-17-frank.chang@sifive.com (mailing list archive)
State New, archived
Headers show
Series target/riscv: support vector extension v1.0 | expand

Commit Message

Frank Chang Aug. 6, 2020, 10:46 a.m. UTC 
From: Frank Chang <frank.chang@sifive.com>

If a 16-bit input is not properly nanboxed, then the input is replaced
with the default qnan.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/translate.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Richard Henderson Aug. 6, 2020, 10:57 p.m. UTC | #1 
On 8/6/20 3:46 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
> 
> If a 16-bit input is not properly nanboxed, then the input is replaced
> with the default qnan.
> 
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/translate.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)

The code is perfectly fine, but the patch has to be merged with the first user
of gen_check_nanbox_h.  Otherwise a bisection that stops at this patch will
Werror for the unused function.


r~
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Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 24026f901d1..95921296a56 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -110,6 +110,16 @@  static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
  *
  * Here, the result is always nan-boxed, even the canonical nan.
  */
+static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)
+{
+    TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull);
+    TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull);
+
+    tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
+    tcg_temp_free_i64(t_max);
+    tcg_temp_free_i64(t_nan);
+}
+
 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
 {
     TCGv_i64 t_max = tcg_const_i64(0xffffffff00000000ull);