| Message ID | 20200817155757.3372-7-roger.pau@citrix.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | x86: switch default MSR behavior | expand |
On 17/08/2020 16:57, Roger Pau Monne wrote: > Linux PV guests will attempt to read the FEATURE_CONTROL MSR, report > no features enabled or available, and that the MSR is already locked. > > Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> > --- > xen/arch/x86/pv/emul-priv-op.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c > index 554a95ae8d..76c878b677 100644 > --- a/xen/arch/x86/pv/emul-priv-op.c > +++ b/xen/arch/x86/pv/emul-priv-op.c > @@ -879,6 +879,10 @@ static int read_msr(unsigned int reg, uint64_t *val, > *val |= APIC_BASE_BSP; > return X86EMUL_OKAY; > > + case MSR_IA32_FEATURE_CONTROL: > + *val = IA32_FEATURE_CONTROL_LOCK; > + return X86EMUL_OKAY; This isn't quite right. This is an Intel-like MSR only, and should #GP for AMD/Hygon. It would be better to move it to the common guest_rdmsr() function, as the two helpers (vmce_lmce, and nested_virt) used to construct it in the vmx code are already generic. This also helps progress the work to drop all the legacy MSR handling. ~Andrew
diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 554a95ae8d..76c878b677 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -879,6 +879,10 @@ static int read_msr(unsigned int reg, uint64_t *val, *val |= APIC_BASE_BSP; return X86EMUL_OKAY; + case MSR_IA32_FEATURE_CONTROL: + *val = IA32_FEATURE_CONTROL_LOCK; + return X86EMUL_OKAY; + case MSR_FS_BASE: if ( is_pv_32bit_domain(currd) ) break;
Linux PV guests will attempt to read the FEATURE_CONTROL MSR, report no features enabled or available, and that the MSR is already locked. Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> --- xen/arch/x86/pv/emul-priv-op.c | 4 ++++ 1 file changed, 4 insertions(+)