| Message ID | 20200815182223.408965-1-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 2ff4b1ed68a45937581e91d0c70bd52a395a5c09 |
| Headers | show |
| Series | ARM: dts: meson: move the L2 cache-controller inside the SoC node | expand |
On 15/08/2020 20:22, Martin Blumenstingl wrote: > All IO mapped SoC peripherals should be within the "soc" node. Move the > L2 cache-controller there as well since it's the only one not following > this pattern. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > --- > arch/arm/boot/dts/meson.dtsi | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi > index eadb0832bcfc..7649dd1e0b9e 100644 > --- a/arch/arm/boot/dts/meson.dtsi > +++ b/arch/arm/boot/dts/meson.dtsi > @@ -11,13 +11,6 @@ / { > #size-cells = <1>; > interrupt-parent = <&gic>; > > - L2: cache-controller@c4200000 { > - compatible = "arm,pl310-cache"; > - reg = <0xc4200000 0x1000>; > - cache-unified; > - cache-level = <2>; > - }; > - > soc { > compatible = "simple-bus"; > #address-cells = <1>; > @@ -172,6 +165,13 @@ timer_abcde: timer@9940 { > }; > }; > > + L2: cache-controller@c4200000 { > + compatible = "arm,pl310-cache"; > + reg = <0xc4200000 0x1000>; > + cache-unified; > + cache-level = <2>; > + }; > + > periph: bus@c4300000 { > compatible = "simple-bus"; > reg = <0xc4300000 0x10000>; > Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes: > All IO mapped SoC peripherals should be within the "soc" node. Move the > L2 cache-controller there as well since it's the only one not following > this pattern. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Boot tested on meson8b-odroidc1 Tested-by: Kevin Hilman <khilman@baylibre.com> Queuing for v5.10. Thanks, Kevin
On Sat, 15 Aug 2020 20:22:23 +0200, Martin Blumenstingl wrote: > All IO mapped SoC peripherals should be within the "soc" node. Move the > L2 cache-controller there as well since it's the only one not following > this pattern. Applied, thanks! [1/1] ARM: dts: meson: move the L2 cache-controller inside the SoC node commit: 8bcbcdb7293cc24eb7b24b67ef2b29b3a45a49e0 Best regards,
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index eadb0832bcfc..7649dd1e0b9e 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -11,13 +11,6 @@ / { #size-cells = <1>; interrupt-parent = <&gic>; - L2: cache-controller@c4200000 { - compatible = "arm,pl310-cache"; - reg = <0xc4200000 0x1000>; - cache-unified; - cache-level = <2>; - }; - soc { compatible = "simple-bus"; #address-cells = <1>; @@ -172,6 +165,13 @@ timer_abcde: timer@9940 { }; }; + L2: cache-controller@c4200000 { + compatible = "arm,pl310-cache"; + reg = <0xc4200000 0x1000>; + cache-unified; + cache-level = <2>; + }; + periph: bus@c4300000 { compatible = "simple-bus"; reg = <0xc4300000 0x10000>;
All IO mapped SoC peripherals should be within the "soc" node. Move the L2 cache-controller there as well since it's the only one not following this pattern. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- arch/arm/boot/dts/meson.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)