@@ -218,7 +218,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = alpha_cpu_class_by_name;
cc->has_work = alpha_cpu_has_work;
cc->do_interrupt = alpha_cpu_do_interrupt;
- cc->cpu_exec_interrupt = alpha_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = alpha_cpu_exec_interrupt_locked;
cc->dump_state = alpha_cpu_dump_state;
cc->set_pc = alpha_cpu_set_pc;
cc->gdb_read_register = alpha_cpu_gdb_read_register;
@@ -277,7 +277,7 @@ extern const VMStateDescription vmstate_alpha_cpu;
#endif
void alpha_cpu_do_interrupt(CPUState *cpu);
-bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req);
+bool alpha_cpu_exec_interrupt_locked(CPUState *cpu, int int_req);
void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags);
hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -414,7 +414,7 @@ void alpha_cpu_do_interrupt(CPUState *cs)
qemu_mutex_unlock_iothread();
}
-bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool alpha_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
AlphaCPU *cpu = ALPHA_CPU(cs);
CPUAlphaState *env = &cpu->env;
@@ -524,7 +524,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
return unmasked || pstate_unmasked;
}
-bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool arm_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
ARMCPUClass *acc = ARM_CPU_GET_CLASS(cs);
CPUARMState *env = cs->env_ptr;
@@ -2217,7 +2217,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = arm_cpu_class_by_name;
cc->has_work = arm_cpu_has_work;
- cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = arm_cpu_exec_interrupt_locked;
cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc;
cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
@@ -995,7 +995,7 @@ void arm_cpu_do_interrupt(CPUState *cpu);
void arm_cpu_do_interrupt_locked(CPUState *cpu);
void arm_v7m_cpu_do_interrupt(CPUState *cpu);
void arm_v7m_cpu_do_interrupt_locked(CPUState *cpu);
-bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
+bool arm_cpu_exec_interrupt_locked(CPUState *cpu, int int_req);
hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
@@ -782,7 +782,7 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
- cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = arm_cpu_exec_interrupt_locked;
cc->gdb_read_register = aarch64_cpu_gdb_read_register;
cc->gdb_write_register = aarch64_cpu_gdb_write_register;
cc->gdb_num_core_regs = 34;
@@ -15,7 +15,8 @@
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+static bool arm_v7m_cpu_exec_interrupt_locked(CPUState *cs,
+ int interrupt_request)
{
ARMCPUClass *acc = ARM_CPU_GET_CLASS(cs);
ARMCPU *cpu = ARM_CPU(cs);
@@ -605,7 +606,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
acc->do_interrupt_locked = arm_v7m_cpu_do_interrupt_locked;
#endif
- cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt_locked;
cc->gdb_core_xml_file = "arm-m-profile.xml";
}
@@ -198,7 +198,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = avr_cpu_has_work;
cc->do_interrupt = avr_cpu_do_interrupt;
- cc->cpu_exec_interrupt = avr_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = avr_cpu_exec_interrupt_locked;
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
@@ -157,7 +157,7 @@ typedef struct AVRCPU {
extern const struct VMStateDescription vms_avr_cpu;
void avr_cpu_do_interrupt(CPUState *cpu);
-bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);
+bool avr_cpu_exec_interrupt_locked(CPUState *cpu, int int_req);
hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
@@ -26,7 +26,7 @@
static void avr_cpu_do_interrupt_locked(CPUState *cs);
-bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool avr_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
bool ret = false;
AVRCPU *cpu = AVR_CPU(cs);
@@ -270,7 +270,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = cris_cpu_has_work;
cc->do_interrupt = cris_cpu_do_interrupt;
ccc->do_interrupt_locked = cris_cpu_do_interrupt_locked;
- cc->cpu_exec_interrupt = cris_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = cris_cpu_exec_interrupt_locked;
cc->dump_state = cris_cpu_dump_state;
cc->set_pc = cris_cpu_set_pc;
cc->gdb_read_register = cris_cpu_gdb_read_register;
@@ -190,7 +190,7 @@ extern const VMStateDescription vmstate_cris_cpu;
void cris_cpu_do_interrupt(CPUState *cpu);
void cris_cpu_do_interrupt_locked(CPUState *cpu);
void crisv10_cpu_do_interrupt_locked(CPUState *cpu);
-bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req);
+bool cris_cpu_exec_interrupt_locked(CPUState *cpu, int int_req);
void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags);
@@ -296,7 +296,7 @@ hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
}
#endif
-bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool cris_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
CRISCPUClass *ccc = CRIS_CPU_CLASS(cs);
CRISCPU *cpu = CRIS_CPU(cs);
@@ -140,7 +140,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = hppa_cpu_class_by_name;
cc->has_work = hppa_cpu_has_work;
cc->do_interrupt = hppa_cpu_do_interrupt;
- cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt_locked;
cc->dump_state = hppa_cpu_dump_state;
cc->set_pc = hppa_cpu_set_pc;
cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb;
@@ -324,7 +324,7 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void hppa_cpu_do_interrupt(CPUState *cpu);
-bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
+bool hppa_cpu_exec_interrupt_locked(CPUState *cpu, int int_req);
void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);
bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
@@ -253,7 +253,7 @@ void hppa_cpu_do_interrupt(CPUState *cs)
qemu_mutex_unlock_iothread();
}
-bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool hppa_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
#ifndef CONFIG_USER_ONLY
HPPACPU *cpu = HPPA_CPU(cs);
@@ -7298,7 +7298,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->has_work = x86_cpu_has_work;
#ifdef CONFIG_TCG
cc->do_interrupt = x86_cpu_do_interrupt;
- cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = x86_cpu_exec_interrupt_locked;
#endif
cc->dump_state = x86_cpu_dump_state;
cc->set_pc = x86_cpu_set_pc;
@@ -1771,7 +1771,7 @@ extern VMStateDescription vmstate_x86_cpu;
* @cpu: vCPU the interrupt is to be handled by.
*/
void x86_cpu_do_interrupt(CPUState *cpu);
-bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
+bool x86_cpu_exec_interrupt_locked(CPUState *cpu, int int_req);
int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -1322,7 +1322,7 @@ void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw)
do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw);
}
-bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool x86_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
@@ -223,7 +223,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = lm32_cpu_class_by_name;
cc->has_work = lm32_cpu_has_work;
cc->do_interrupt = lm32_cpu_do_interrupt;
- cc->cpu_exec_interrupt = lm32_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = lm32_cpu_exec_interrupt_locked;
cc->dump_state = lm32_cpu_dump_state;
cc->set_pc = lm32_cpu_set_pc;
cc->gdb_read_register = lm32_cpu_gdb_read_register;
@@ -199,7 +199,7 @@ extern const VMStateDescription vmstate_lm32_cpu;
#endif
void lm32_cpu_do_interrupt(CPUState *cpu);
-bool lm32_cpu_exec_interrupt(CPUState *cs, int int_req);
+bool lm32_cpu_exec_interrupt_locked(CPUState *cs, int int_req);
void lm32_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int lm32_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -205,7 +205,7 @@ void lm32_cpu_do_interrupt(CPUState *cs)
qemu_mutex_unlock_iothread();
}
-bool lm32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool lm32_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
LM32CPU *cpu = LM32_CPU(cs);
CPULM32State *env = &cpu->env;
@@ -278,7 +278,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = m68k_cpu_class_by_name;
cc->has_work = m68k_cpu_has_work;
cc->do_interrupt = m68k_cpu_do_interrupt;
- cc->cpu_exec_interrupt = m68k_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = m68k_cpu_exec_interrupt_locked;
cc->dump_state = m68k_cpu_dump_state;
cc->set_pc = m68k_cpu_set_pc;
cc->gdb_read_register = m68k_cpu_gdb_read_register;
@@ -165,7 +165,7 @@ struct M68kCPU {
void m68k_cpu_do_interrupt(CPUState *cpu);
-bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
+bool m68k_cpu_exec_interrupt_locked(CPUState *cpu, int int_req);
void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -511,7 +511,7 @@ void m68k_cpu_do_interrupt(CPUState *cs)
qemu_mutex_unlock_iothread();
}
-bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool m68k_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
M68kCPU *cpu = M68K_CPU(cs);
CPUM68KState *env = &cpu->env;
@@ -317,7 +317,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = mb_cpu_class_by_name;
cc->has_work = mb_cpu_has_work;
cc->do_interrupt = mb_cpu_do_interrupt;
- cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = mb_cpu_exec_interrupt_locked;
cc->dump_state = mb_cpu_dump_state;
cc->set_pc = mb_cpu_set_pc;
cc->gdb_read_register = mb_cpu_gdb_read_register;
@@ -316,7 +316,7 @@ struct MicroBlazeCPU {
void mb_cpu_do_interrupt(CPUState *cs);
-bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
+bool mb_cpu_exec_interrupt_locked(CPUState *cs, int int_req);
void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -294,7 +294,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
qemu_mutex_unlock_iothread();
}
-bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool mb_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
CPUMBState *env = &cpu->env;
@@ -197,7 +197,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work_with_iothread_lock = mips_cpu_has_work;
cc->do_interrupt = mips_cpu_do_interrupt;
- cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = mips_cpu_exec_interrupt_locked;
cc->dump_state = mips_cpu_dump_state;
cc->set_pc = mips_cpu_set_pc;
cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
@@ -1405,7 +1405,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
qemu_mutex_unlock_iothread();
}
-bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool mips_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
MIPSCPU *cpu = MIPS_CPU(cs);
@@ -81,7 +81,7 @@ enum CPUMIPSMSADataFormat {
};
void mips_cpu_do_interrupt(CPUState *cpu);
-bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
+bool mips_cpu_exec_interrupt_locked(CPUState *cpu, int int_req);
void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -98,7 +98,7 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
ncc->parent_realize(dev, errp);
}
-static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+static bool nios2_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
CPUNios2State *env = &cpu->env;
@@ -193,7 +193,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = nios2_cpu_class_by_name;
cc->has_work = nios2_cpu_has_work;
cc->do_interrupt = nios2_cpu_do_interrupt;
- cc->cpu_exec_interrupt = nios2_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = nios2_cpu_exec_interrupt_locked;
cc->dump_state = nios2_cpu_dump_state;
cc->set_pc = nios2_cpu_set_pc;
cc->disas_set_info = nios2_cpu_disas_set_info;
@@ -155,7 +155,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = openrisc_cpu_class_by_name;
cc->has_work = openrisc_cpu_has_work;
cc->do_interrupt = openrisc_cpu_do_interrupt;
- cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt_locked;
cc->dump_state = openrisc_cpu_dump_state;
cc->set_pc = openrisc_cpu_set_pc;
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
@@ -317,7 +317,7 @@ typedef struct OpenRISCCPU {
void cpu_openrisc_list(void);
void openrisc_cpu_do_interrupt(CPUState *cpu);
-bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
+bool openrisc_cpu_exec_interrupt_locked(CPUState *cpu, int int_req);
void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -108,7 +108,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
qemu_mutex_unlock_iothread();
}
-bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool openrisc_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUOpenRISCState *env = &cpu->env;
@@ -1233,7 +1233,7 @@ struct PPCVirtualHypervisorClass {
void ppc_cpu_do_interrupt(CPUState *cpu);
void ppc_cpu_do_interrupt_locked(CPUState *cpu);
-bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
+bool ppc_cpu_exec_interrupt_locked(CPUState *cpu, int int_req);
void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
void ppc_cpu_dump_statistics(CPUState *cpu, int flags);
hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
@@ -1052,7 +1052,7 @@ void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector)
}
#endif /* !CONFIG_USER_ONLY */
-bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool ppc_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
@@ -10886,7 +10886,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->parse_features = ppc_cpu_parse_featurestr;
cc->has_work_with_iothread_lock = ppc_cpu_has_work;
cc->do_interrupt = ppc_cpu_do_interrupt;
- cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt_locked;
cc->dump_state = ppc_cpu_dump_state;
cc->dump_statistics = ppc_cpu_dump_statistics;
cc->set_pc = ppc_cpu_set_pc;
@@ -538,7 +538,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = riscv_cpu_class_by_name;
cc->has_work_with_iothread_lock = riscv_cpu_has_work;
cc->do_interrupt = riscv_cpu_do_interrupt;
- cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt_locked;
cc->dump_state = riscv_cpu_dump_state;
cc->set_pc = riscv_cpu_set_pc;
cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
@@ -315,7 +315,7 @@ extern const char * const riscv_intr_names[];
void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
+bool riscv_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
@@ -78,7 +78,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
}
#endif
-bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool riscv_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
#if !defined(CONFIG_USER_ONLY)
if (interrupt_request & CPU_INTERRUPT_HARD) {
@@ -186,7 +186,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->class_by_name = rx_cpu_class_by_name;
cc->has_work = rx_cpu_has_work;
cc->do_interrupt = rx_cpu_do_interrupt;
- cc->cpu_exec_interrupt = rx_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = rx_cpu_exec_interrupt_locked;
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
cc->synchronize_from_tb = rx_cpu_synchronize_from_tb;
@@ -127,7 +127,7 @@ typedef RXCPU ArchCPU;
const char *rx_crname(uint8_t cr);
void rx_cpu_do_interrupt(CPUState *cpu);
void rx_cpu_do_interrupt_locked(CPUState *cpu);
-bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req);
+bool rx_cpu_exec_interrupt_locked(CPUState *cpu, int int_req);
void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
@@ -126,7 +126,7 @@ void rx_cpu_do_interrupt(CPUState *cs)
qemu_mutex_unlock_iothread();
}
-bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool rx_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
RXCPU *cpu = RXCPU(cs);
CPURXState *env = &cpu->env;
@@ -505,7 +505,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
#ifdef CONFIG_TCG
- cc->cpu_exec_interrupt = s390_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = s390_cpu_exec_interrupt_locked;
cc->debug_excp_handler = s390x_cpu_debug_excp_handler;
cc->do_unaligned_access = s390x_cpu_do_unaligned_access;
#endif
@@ -543,7 +543,7 @@ try_deliver:
}
}
-bool s390_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool s390_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
S390CPU *cpu = S390_CPU(cs);
@@ -270,7 +270,7 @@ ObjectClass *s390_cpu_class_by_name(const char *name);
void s390x_cpu_debug_excp_handler(CPUState *cs);
void s390_cpu_do_interrupt(CPUState *cpu);
void s390_cpu_do_interrupt_locked(CPUState *cpu);
-bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
+bool s390_cpu_exec_interrupt_locked(CPUState *cpu, int int_req);
bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
@@ -219,7 +219,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = superh_cpu_class_by_name;
cc->has_work = superh_cpu_has_work;
cc->do_interrupt = superh_cpu_do_interrupt;
- cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = superh_cpu_exec_interrupt_locked;
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
@@ -205,7 +205,7 @@ struct SuperHCPU {
void superh_cpu_do_interrupt(CPUState *cpu);
-bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
+bool superh_cpu_exec_interrupt_locked(CPUState *cpu, int int_req);
void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
@@ -789,7 +789,7 @@ void superh_cpu_do_interrupt(CPUState *cs)
qemu_mutex_unlock_iothread();
}
-bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool superh_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
SuperHCPU *cpu = SUPERH_CPU(cs);
@@ -77,7 +77,7 @@ static void sparc_cpu_reset(DeviceState *dev)
env->cache_control = 0;
}
-static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+static bool sparc_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
SPARCCPU *cpu = SPARC_CPU(cs);
@@ -864,7 +864,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->parse_features = sparc_cpu_parse_features;
cc->has_work_with_iothread_lock = sparc_cpu_has_work;
cc->do_interrupt = sparc_cpu_do_interrupt;
- cc->cpu_exec_interrupt = sparc_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = sparc_cpu_exec_interrupt_locked;
cc->dump_state = sparc_cpu_dump_state;
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
@@ -132,7 +132,8 @@ static void tilegx_cpu_do_interrupt(CPUState *cs)
qemu_mutex_unlock_iothread();
}
-static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+static bool tilegx_cpu_exec_interrupt_locked(CPUState *cs,
+ int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
tilegx_cpu_do_interrupt_locked(cs);
@@ -155,7 +156,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = tilegx_cpu_class_by_name;
cc->has_work = tilegx_cpu_has_work;
cc->do_interrupt = tilegx_cpu_do_interrupt;
- cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt_locked;
cc->dump_state = tilegx_cpu_dump_state;
cc->set_pc = tilegx_cpu_set_pc;
cc->tlb_fill = tilegx_cpu_tlb_fill;
@@ -132,7 +132,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = uc32_cpu_class_by_name;
cc->has_work = uc32_cpu_has_work;
cc->do_interrupt = uc32_cpu_do_interrupt;
- cc->cpu_exec_interrupt = uc32_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = uc32_cpu_exec_interrupt_locked;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
cc->tlb_fill = uc32_cpu_tlb_fill;
@@ -77,7 +77,7 @@ struct UniCore32CPU {
void uc32_cpu_do_interrupt(CPUState *cpu);
void uc32_cpu_do_interrupt_locked(CPUState *cpu);
-bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req);
+bool uc32_cpu_exec_interrupt_locked(CPUState *cpu, int int_req);
void uc32_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr uc32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
@@ -167,7 +167,7 @@ void helper_cp1_putc(target_ulong regval)
}
#endif /* !CONFIG_USER_ONLY */
-bool uc32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool uc32_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
UniCore32CPU *cpu = UNICORE32_CPU(cs);
@@ -191,7 +191,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = xtensa_cpu_class_by_name;
cc->has_work_with_iothread_lock = xtensa_cpu_has_work;
cc->do_interrupt = xtensa_cpu_do_interrupt;
- cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
+ cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt_locked;
cc->dump_state = xtensa_cpu_dump_state;
cc->set_pc = xtensa_cpu_set_pc;
cc->gdb_read_register = xtensa_cpu_gdb_read_register;
@@ -564,7 +564,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
void xtensa_cpu_do_interrupt(CPUState *cpu);
-bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
+bool xtensa_cpu_exec_interrupt_locked(CPUState *cpu, int interrupt_request);
void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
unsigned size, MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
@@ -266,7 +266,7 @@ void xtensa_cpu_do_interrupt(CPUState *cs)
qemu_mutex_unlock_iothread();
}
-bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+bool xtensa_cpu_exec_interrupt_locked(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
cs->exception_index = EXC_IRQ;
The rename of all *_cpu_exec_interrupt functions to *_cpu_exec_interrupt_locked is preparation for pushing the BQL lock around these functions down into the per-arch implementation of *_cpu_exec_interrupt. In a later patch, which pushes down the lock, we will add a new *_cpu_exec_interrupt function, which grabs the BQL and calls to *_cpu_exec_interrupt_locked. This patch is part of a series of transitions to move the BQL down into the cpu_exec_interrupt per arch functions. This set of transitions is needed to maintain bisectability. The purpose of this set of changes is to set the groundwork so that an arch could move towards removing the BQL from the cpu_handle_interrupt/exception paths. This approach was suggested by Paolo Bonzini. For reference, here are key posts in the discussion, explaining the reasoning/benefits of this approach. https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg00784.html https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg01517.html https://lists.gnu.org/archive/html/qemu-devel/2020-07/msg08731.html https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg00044.html Signed-off-by: Robert Foley <robert.foley@linaro.org> --- target/alpha/cpu.c | 2 +- target/alpha/cpu.h | 2 +- target/alpha/helper.c | 2 +- target/arm/cpu.c | 4 ++-- target/arm/cpu.h | 2 +- target/arm/cpu64.c | 2 +- target/arm/cpu_tcg.c | 5 +++-- target/avr/cpu.c | 2 +- target/avr/cpu.h | 2 +- target/avr/helper.c | 2 +- target/cris/cpu.c | 2 +- target/cris/cpu.h | 2 +- target/cris/helper.c | 2 +- target/hppa/cpu.c | 2 +- target/hppa/cpu.h | 2 +- target/hppa/int_helper.c | 2 +- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 +- target/i386/seg_helper.c | 2 +- target/lm32/cpu.c | 2 +- target/lm32/cpu.h | 2 +- target/lm32/helper.c | 2 +- target/m68k/cpu.c | 2 +- target/m68k/cpu.h | 2 +- target/m68k/op_helper.c | 2 +- target/microblaze/cpu.c | 2 +- target/microblaze/cpu.h | 2 +- target/microblaze/helper.c | 2 +- target/mips/cpu.c | 2 +- target/mips/helper.c | 2 +- target/mips/internal.h | 2 +- target/nios2/cpu.c | 4 ++-- target/openrisc/cpu.c | 2 +- target/openrisc/cpu.h | 2 +- target/openrisc/interrupt.c | 2 +- target/ppc/cpu.h | 2 +- target/ppc/excp_helper.c | 2 +- target/ppc/translate_init.inc.c | 2 +- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/cpu_helper.c | 2 +- target/rx/cpu.c | 2 +- target/rx/cpu.h | 2 +- target/rx/helper.c | 2 +- target/s390x/cpu.c | 2 +- target/s390x/excp_helper.c | 2 +- target/s390x/internal.h | 2 +- target/sh4/cpu.c | 2 +- target/sh4/cpu.h | 2 +- target/sh4/helper.c | 2 +- target/sparc/cpu.c | 4 ++-- target/tilegx/cpu.c | 5 +++-- target/unicore32/cpu.c | 2 +- target/unicore32/cpu.h | 2 +- target/unicore32/helper.c | 2 +- target/xtensa/cpu.c | 2 +- target/xtensa/cpu.h | 2 +- target/xtensa/exc_helper.c | 2 +- 58 files changed, 65 insertions(+), 63 deletions(-)