| Message ID | 20200907120852.12090-2-jianjun.wang@mediatek.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | PCI: mediatek: Add new generation controller support | expand |
On Mon, 07 Sep 2020 20:08:50 +0800, Jianjun Wang wrote: > Add YAML schemas documentation for Gen3 PCIe controller on > MediaTek SoCs. > > Acked-by: Ryder Lee <ryder.lee@mediatek.com> > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > --- > .../bindings/pci/mediatek-pcie-gen3.yaml | 158 ++++++++++++++++++ > 1 file changed, 158 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > My bot found errors running 'make dt_binding_check' on your patch: Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.example.dts:55.56-59.19: Warning (pci_device_reg): /example-0/bus/pcie@11230000/legacy-interrupt-controller: missing PCI reg property See https://patchwork.ozlabs.org/patch/1359119 If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure dt-schema is up to date: pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade Please check and re-submit.
On Mon, Sep 07, 2020 at 08:08:50PM +0800, Jianjun Wang wrote: > Add YAML schemas documentation for Gen3 PCIe controller on > MediaTek SoCs. Please mention "mediatek" in the subject line so "git log --oneline" is more useful. The convention (not universally observed) seems to be something like: dt-bindings: PCI: <driver-name>: Add YAML schema
On Mon, Sep 07, 2020 at 08:08:50PM +0800, Jianjun Wang wrote: > Add YAML schemas documentation for Gen3 PCIe controller on > MediaTek SoCs. dt-bindings: PCI: mediatek: ... for the subject. > > Acked-by: Ryder Lee <ryder.lee@mediatek.com> > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > --- > .../bindings/pci/mediatek-pcie-gen3.yaml | 158 ++++++++++++++++++ > 1 file changed, 158 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > new file mode 100644 > index 000000000000..108d29259c05 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > @@ -0,0 +1,158 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Gen3 PCIe controller on MediaTek SoCs > + > +maintainers: > + - Jianjun Wang <jianjun.wang@mediatek.com> > + > +allOf: > + - $ref: /schemas/pci/pci-bus.yaml# > + > +properties: > + compatible: > + oneOf: > + - const: mediatek,gen3-pcie > + - const: mediatek,mt8192-pcie > + > + device_type: > + const: pci > + > + "#address-cells": > + const: 3 > + > + "#size-cells": > + const: 2 Can drop these 3. Already in pci-bus.yaml. > + > + reg: > + items: > + - description: Controller control and status registers. Just 'maxItems: 1'. The description doesn't add any value. > + > + reg-names: > + items: > + - const: pcie-mac Don't really need a name here. > + > + interrupts: > + maxItems: 1 > + > + bus-range: > + description: Range of bus numbers associated with this controller. > + > + ranges: > + minItems: 1 > + maxItems: 8 > + > + resets: > + minItems: 1 > + maxItems: 2 > + > + reset-names: > + anyOf: > + - const: mac-rst > + - const: phy-rst Doesn't the PHY's reset belong in the PHY node? > + > + clocks: > + maxItems: 5 > + > + assigned-clocks: > + maxItems: 1 > + > + assigned-clock-parents: > + maxItems: 1 > + > + phys: > + maxItems: 1 > + > + phy-names: > + const: pcie-phy Not really a useful name and there's only one. Please drop. > + > + '#interrupt-cells': > + const: 1 > + > + interrupt-map-mask: > + description: Standard PCI IRQ mapping properties. > + > + interrupt-map: > + description: Standard PCI IRQ mapping properties. Can drop these. > + > + legacy-interrupt-controller: Just 'interrupt-controller' And don't copy the same bug of using 'of_get_next_child'. You should get the child node by name. > + description: Interrupt controller node for handling legacy PCI interrupts. > + type: object > + properties: > + "#address-cells": > + const: 0 > + "#interrupt-cells": > + const: 1 > + interrupt-controller: true > + > + required: > + - "#address-cells" > + - "#interrupt-cells" > + - interrupt-controller additionalProperties: false > + > +required: > + - compatible > + - device_type > + - "#address-cells" > + - "#size-cells" Don't need these, pci-bus.yaml already requires them. > + - reg > + - reg-names > + - bus-range If the range is 0-0xff, then this isn't really required. > + - interrupts > + - ranges > + - clocks > + - '#interrupt-cells' > + - interrupt-map > + - interrupt-map-mask > + - legacy-interrupt-controller > + > +additionalProperties: false unevaluatedProperties: false (Should be used when including a ref (pci-bus.yaml).) > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pcie: pcie@11230000 { > + compatible = "mediatek,mt8192-pcie"; > + device_type = "pci"; > + #address-cells = <3>; > + #size-cells = <2>; > + reg = <0x00 0x11230000 0x00 0x4000>; > + reg-names = "pcie-mac"; > + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; > + bus-range = <0x00 0xff>; > + ranges = <0x82000000 0x00 0x12000000 0x00 0x12000000 0x00 0x1000000>; > + clocks = <&infracfg 40>, > + <&infracfg 43>, > + <&infracfg 97>, > + <&infracfg 99>, > + <&infracfg 111>; > + assigned-clocks = <&topckgen 50>; > + assigned-clock-parents = <&topckgen 91>; > + > + phys = <&pciephy>; > + phy-names = "pcie-phy"; > + resets = <&infracfg_rst 0>; > + reset-names = "phy-rst"; > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &pcie_intc 0>, > + <0 0 0 2 &pcie_intc 1>, > + <0 0 0 3 &pcie_intc 2>, > + <0 0 0 4 &pcie_intc 3>; > + pcie_intc: legacy-interrupt-controller { > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-controller; > + }; > + }; > + }; > -- > 2.25.1
On Tue, 2020-09-08 at 13:50 -0600, Rob Herring wrote: > On Mon, 07 Sep 2020 20:08:50 +0800, Jianjun Wang wrote: > > Add YAML schemas documentation for Gen3 PCIe controller on > > MediaTek SoCs. > > > > Acked-by: Ryder Lee <ryder.lee@mediatek.com> > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > > --- > > .../bindings/pci/mediatek-pcie-gen3.yaml | 158 ++++++++++++++++++ > > 1 file changed, 158 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > > > > My bot found errors running 'make dt_binding_check' on your patch: > > Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.example.dts:55.56-59.19: Warning (pci_device_reg): /example-0/bus/pcie@11230000/legacy-interrupt-controller: missing PCI reg property > > > See https://patchwork.ozlabs.org/patch/1359119 > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure dt-schema is up to date: > > pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade > > Please check and re-submit. > Yes, I have already found this warning message, but I'm confused with how to add this reg property, since the interrupt-controller has inherit the pci device type but does not have its own registers. Could you please tell me how to fix this error, or which docs can I refer to? Thanks.
On Tue, 2020-09-08 at 15:04 -0500, Bjorn Helgaas wrote: > On Mon, Sep 07, 2020 at 08:08:50PM +0800, Jianjun Wang wrote: > > Add YAML schemas documentation for Gen3 PCIe controller on > > MediaTek SoCs. > > Please mention "mediatek" in the subject line so "git log --oneline" > is more useful. > > The convention (not universally observed) seems to be something like: > > dt-bindings: PCI: <driver-name>: Add YAML schema Thanks for your review, I will fix it in the next version.
On Tue, 2020-09-08 at 14:21 -0600, Rob Herring wrote: > On Mon, Sep 07, 2020 at 08:08:50PM +0800, Jianjun Wang wrote: > > Add YAML schemas documentation for Gen3 PCIe controller on > > MediaTek SoCs. > > dt-bindings: PCI: mediatek: ... for the subject. > > > > > Acked-by: Ryder Lee <ryder.lee@mediatek.com> > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > > --- > > .../bindings/pci/mediatek-pcie-gen3.yaml | 158 ++++++++++++++++++ > > 1 file changed, 158 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > > > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > new file mode 100644 > > index 000000000000..108d29259c05 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > @@ -0,0 +1,158 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Gen3 PCIe controller on MediaTek SoCs > > + > > +maintainers: > > + - Jianjun Wang <jianjun.wang@mediatek.com> > > + > > +allOf: > > + - $ref: /schemas/pci/pci-bus.yaml# > > + > > +properties: > > + compatible: > > + oneOf: > > + - const: mediatek,gen3-pcie > > + - const: mediatek,mt8192-pcie > > + > > > + device_type: > > + const: pci > > + > > + "#address-cells": > > + const: 3 > > + > > + "#size-cells": > > + const: 2 > > Can drop these 3. Already in pci-bus.yaml. > > > + > > + reg: > > + items: > > + - description: Controller control and status registers. > > Just 'maxItems: 1'. The description doesn't add any value. > > > + > > + reg-names: > > + items: > > + - const: pcie-mac > > Don't really need a name here. > > > + > > + interrupts: > > + maxItems: 1 > > + > > + bus-range: > > + description: Range of bus numbers associated with this controller. > > + > > + ranges: > > + minItems: 1 > > + maxItems: 8 > > + > > + resets: > > + minItems: 1 > > + maxItems: 2 > > + > > + reset-names: > > + anyOf: > > + - const: mac-rst > > + - const: phy-rst > > Doesn't the PHY's reset belong in the PHY node? There are some cases that we don't need the PHY driver, but for the reason of power saving, the HW still remain the PHY's reset in infra domain and it will be asserted before kernel stage, so we still need to release this reset in the PCIe MAC driver. > > > + > > + clocks: > > + maxItems: 5 > > + > > + assigned-clocks: > > + maxItems: 1 > > + > > + assigned-clock-parents: > > + maxItems: 1 > > + > > + phys: > > + maxItems: 1 > > + > > + phy-names: > > + const: pcie-phy > > Not really a useful name and there's only one. Please drop. > > > + > > + '#interrupt-cells': > > + const: 1 > > + > > > + interrupt-map-mask: > > + description: Standard PCI IRQ mapping properties. > > + > > + interrupt-map: > > + description: Standard PCI IRQ mapping properties. > > Can drop these. > > > + > > + legacy-interrupt-controller: > > Just 'interrupt-controller' > > And don't copy the same bug of using 'of_get_next_child'. You should get > the child node by name. > > > + description: Interrupt controller node for handling legacy PCI interrupts. > > + type: object > > + properties: > > + "#address-cells": > > + const: 0 > > + "#interrupt-cells": > > + const: 1 > > + interrupt-controller: true > > + > > + required: > > + - "#address-cells" > > + - "#interrupt-cells" > > + - interrupt-controller > > additionalProperties: false > > > + > > +required: > > + - compatible > > > + - device_type > > + - "#address-cells" > > + - "#size-cells" > > Don't need these, pci-bus.yaml already requires them. > > > + - reg > > + - reg-names > > + - bus-range > > If the range is 0-0xff, then this isn't really required. > > > + - interrupts > > + - ranges > > + - clocks > > + - '#interrupt-cells' > > + - interrupt-map > > + - interrupt-map-mask > > + - legacy-interrupt-controller > > + > > +additionalProperties: false > > unevaluatedProperties: false > > (Should be used when including a ref (pci-bus.yaml).) > > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/interrupt-controller/irq.h> > > + > > + bus { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + pcie: pcie@11230000 { > > + compatible = "mediatek,mt8192-pcie"; > > + device_type = "pci"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + reg = <0x00 0x11230000 0x00 0x4000>; > > + reg-names = "pcie-mac"; > > + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; > > + bus-range = <0x00 0xff>; > > + ranges = <0x82000000 0x00 0x12000000 0x00 0x12000000 0x00 0x1000000>; > > + clocks = <&infracfg 40>, > > + <&infracfg 43>, > > + <&infracfg 97>, > > + <&infracfg 99>, > > + <&infracfg 111>; > > + assigned-clocks = <&topckgen 50>; > > + assigned-clock-parents = <&topckgen 91>; > > + > > + phys = <&pciephy>; > > + phy-names = "pcie-phy"; > > + resets = <&infracfg_rst 0>; > > + reset-names = "phy-rst"; > > + > > + #interrupt-cells = <1>; > > + interrupt-map-mask = <0 0 0 0x7>; > > + interrupt-map = <0 0 0 1 &pcie_intc 0>, > > + <0 0 0 2 &pcie_intc 1>, > > + <0 0 0 3 &pcie_intc 2>, > > + <0 0 0 4 &pcie_intc 3>; > > + pcie_intc: legacy-interrupt-controller { > > + #address-cells = <0>; > > + #interrupt-cells = <1>; > > + interrupt-controller; > > + }; > > + }; > > + }; > > -- > > 2.25.1 > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
On Tue, Sep 8, 2020 at 9:10 PM Jianjun Wang <jianjun.wang@mediatek.com> wrote: > > On Tue, 2020-09-08 at 13:50 -0600, Rob Herring wrote: > > On Mon, 07 Sep 2020 20:08:50 +0800, Jianjun Wang wrote: > > > Add YAML schemas documentation for Gen3 PCIe controller on > > > MediaTek SoCs. > > > > > > Acked-by: Ryder Lee <ryder.lee@mediatek.com> > > > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> > > > --- > > > .../bindings/pci/mediatek-pcie-gen3.yaml | 158 ++++++++++++++++++ > > > 1 file changed, 158 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml > > > > > > > > > My bot found errors running 'make dt_binding_check' on your patch: > > > > Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.example.dts:55.56-59.19: Warning (pci_device_reg): /example-0/bus/pcie@11230000/legacy-interrupt-controller: missing PCI reg property > > > > > > See https://patchwork.ozlabs.org/patch/1359119 > > > > If you already ran 'make dt_binding_check' and didn't see the above > > error(s), then make sure dt-schema is up to date: > > > > pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade > > > > Please check and re-submit. > > > > Yes, I have already found this warning message, but I'm confused with > how to add this reg property, since the interrupt-controller has inherit > the pci device type but does not have its own registers. > > Could you please tell me how to fix this error, or which docs can I > refer to? Actually, disregard this. We need to fix dtc for this case. Rob
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml new file mode 100644 index 000000000000..108d29259c05 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Gen3 PCIe controller on MediaTek SoCs + +maintainers: + - Jianjun Wang <jianjun.wang@mediatek.com> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + oneOf: + - const: mediatek,gen3-pcie + - const: mediatek,mt8192-pcie + + device_type: + const: pci + + "#address-cells": + const: 3 + + "#size-cells": + const: 2 + + reg: + items: + - description: Controller control and status registers. + + reg-names: + items: + - const: pcie-mac + + interrupts: + maxItems: 1 + + bus-range: + description: Range of bus numbers associated with this controller. + + ranges: + minItems: 1 + maxItems: 8 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + anyOf: + - const: mac-rst + - const: phy-rst + + clocks: + maxItems: 5 + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + '#interrupt-cells': + const: 1 + + interrupt-map-mask: + description: Standard PCI IRQ mapping properties. + + interrupt-map: + description: Standard PCI IRQ mapping properties. + + legacy-interrupt-controller: + description: Interrupt controller node for handling legacy PCI interrupts. + type: object + properties: + "#address-cells": + const: 0 + "#interrupt-cells": + const: 1 + interrupt-controller: true + + required: + - "#address-cells" + - "#interrupt-cells" + - interrupt-controller + +required: + - compatible + - device_type + - "#address-cells" + - "#size-cells" + - reg + - reg-names + - bus-range + - interrupts + - ranges + - clocks + - '#interrupt-cells' + - interrupt-map + - interrupt-map-mask + - legacy-interrupt-controller + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie: pcie@11230000 { + compatible = "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x00 0x11230000 0x00 0x4000>; + reg-names = "pcie-mac"; + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0x00 0x12000000 0x00 0x12000000 0x00 0x1000000>; + clocks = <&infracfg 40>, + <&infracfg 43>, + <&infracfg 97>, + <&infracfg 99>, + <&infracfg 111>; + assigned-clocks = <&topckgen 50>; + assigned-clock-parents = <&topckgen 91>; + + phys = <&pciephy>; + phy-names = "pcie-phy"; + resets = <&infracfg_rst 0>; + reset-names = "phy-rst"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + pcie_intc: legacy-interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + };