| Message ID | 1599624552-17523-1-git-send-email-chenhc@lemote.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/3] MIPS: Loongson64: Increase NR_IRQS to 320 | expand |
On 2020-09-09 05:09, Huacai Chen wrote: > Modernized Loongson64 uses a hierarchical organization for interrupt > controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ > numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) > is not enough to represent all interrupts, so let's increase NR_IRQS to > 320. > > Cc: stable@vger.kernel.org > Signed-off-by: Huacai Chen <chenhc@lemote.com> > --- > arch/mips/include/asm/mach-loongson64/irq.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/mips/include/asm/mach-loongson64/irq.h > b/arch/mips/include/asm/mach-loongson64/irq.h > index f5e362f7..0da3017 100644 > --- a/arch/mips/include/asm/mach-loongson64/irq.h > +++ b/arch/mips/include/asm/mach-loongson64/irq.h > @@ -7,7 +7,7 @@ > /* cpu core interrupt numbers */ > #define NR_IRQS_LEGACY 16 > #define NR_MIPS_CPU_IRQS 8 > -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) > +#define NR_IRQS 320 > > #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY Why are you hardcoding a random value instead of bumping the constant in NR_IRQS? M.
Hi
[This is an automated email]
This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all
The bot has tested the following trees: v5.8.7, v5.4.63, v4.19.143, v4.14.196, v4.9.235, v4.4.235.
v5.8.7: Failed to apply! Possible dependencies:
925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout")
v5.4.63: Failed to apply! Possible dependencies:
268a2d600130 ("MIPS: Loongson64: Rename CPU TYPES")
39b2d7565a47 ("MIPS: Kconfig: always select ARC_MEMORY and ARC_PROMLIB for platform")
6fbde6b492df ("MIPS: Loongson64: Move files to the top-level directory")
71e2f4dd5a65 ("MIPS: Fork loongson2ef from loongson64")
7505576d1c1a ("MIPS: add support for SGI Octane (IP30)")
863be3c3ab73 ("MIPS: Add header files reference with path prefix")
8bec3875c547 ("MIPS: Loongson64: Drop legacy IRQ code")
925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout")
v4.19.143: Failed to apply! Possible dependencies:
05a0a3441869 ("rtc: mips: default to rtc-cmos on mips")
69a07a41d908 ("MIPS: SGI-IP27: rework HUB interrupts")
863be3c3ab73 ("MIPS: Add header files reference with path prefix")
925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout")
eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci")
v4.14.196: Failed to apply! Possible dependencies:
3d8757b87d7f ("s390/sthyi: add s390_sthyi system call")
69a07a41d908 ("MIPS: SGI-IP27: rework HUB interrupts")
71406883fd35 ("s390/kexec_file: Add kexec_file_load system call")
840798a1f529 ("s390/kexec_file: Add purgatory")
863be3c3ab73 ("MIPS: Add header files reference with path prefix")
87a4c375995e ("kconfig: include kernel/Kconfig.preempt from init/Kconfig")
8e6d08e0a15e ("openrisc: initial SMP support")
925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout")
9fb6c9b3fea1 ("s390/sthyi: add cache to store hypervisor info")
b7c92f1a4e13 ("s390/sthyi: reorganize sthyi implementation")
c33eff600584 ("s390/perf: add perf_regs support and user stack dump")
e71ea3badae5 ("nds32: Build infrastructure")
eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci")
fbe934d69eb7 ("RISC-V: Build Infrastructure")
v4.9.235: Failed to apply! Possible dependencies:
043b42bcbbc6 ("arch/openrisc: add option to skip DMA sync as a part of mapping")
07c75d7a6b9e ("drivers: dma-mapping: allow dma_common_mmap() for NOMMU")
266c7fad1572 ("openrisc: Consolidate setup to use memblock instead of bootmem")
34bbdcdcda88 ("openrisc: add NR_CPUS Kconfig default value")
3e06a1633930 ("openrisc: add cache way information to cpuinfo")
550116d21a65 ("scripts/spelling.txt: add "aligment" pattern and fix typo instances")
63104c06a9ed ("openrisc: add l.lwa/l.swa emulation")
69a07a41d908 ("MIPS: SGI-IP27: rework HUB interrupts")
6d526ee26ccd ("arm64: mm: enable CONFIG_HOLES_IN_ZONE for NUMA")
7844572c6339 ("lib/dma-noop: Only build dma_noop_ops for s390 and m32r")
863be3c3ab73 ("MIPS: Add header files reference with path prefix")
87a4c375995e ("kconfig: include kernel/Kconfig.preempt from init/Kconfig")
8c9b7db0de3d ("openrisc: head: refactor out tlb flush into it's own function")
8e6d08e0a15e ("openrisc: initial SMP support")
925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout")
da6b21e97e39 ("ARM: Drop fixed 200 Hz timer requirement from Samsung platforms")
e1231b0e487c ("s390: add cma support")
e71ea3badae5 ("nds32: Build infrastructure")
eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci")
v4.4.235: Failed to apply! Possible dependencies:
0d4a619b64ba ("dma-mapping: make the generic coherent dma mmap implementation optional")
1a2db300348b ("arm64, numa: Add NUMA support for arm64 platforms.")
37eda9df5bd8 ("ARC: mm: Introduce explicit super page size support")
42b510eb56de ("h8300: Add LZO compression")
69a07a41d908 ("MIPS: SGI-IP27: rework HUB interrupts")
6d526ee26ccd ("arm64: mm: enable CONFIG_HOLES_IN_ZONE for NUMA")
79387179e2e4 ("parisc: convert to dma_map_ops")
7af3a0a99252 ("arm64/numa: support HAVE_SETUP_PER_CPU_AREA")
863be3c3ab73 ("MIPS: Add header files reference with path prefix")
87a4c375995e ("kconfig: include kernel/Kconfig.preempt from init/Kconfig")
910cd32e552e ("parisc: Fix and enable seccomp filter support")
925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout")
96ff2d7081cf ("h8300: Add KGDB support.")
97a23beb8db9 ("clocksource/drivers/h8300_timer8: Separate the Kconfig option from the arch")
da6b21e97e39 ("ARM: Drop fixed 200 Hz timer requirement from Samsung platforms")
eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci")
fff7fb0b2d90 ("lib/GCD.c: use binary GCD algorithm instead of Euclidean")
NOTE: The patch will not be queued to stable trees until it is upstream.
How should we proceed with this patch?
Hi, Sasha, On Fri, Sep 11, 2020 at 1:21 AM Sasha Levin <sashal@kernel.org> wrote: > > Hi > > [This is an automated email] > > This commit has been processed because it contains a -stable tag. > The stable tag indicates that it's relevant for the following trees: all > > The bot has tested the following trees: v5.8.7, v5.4.63, v4.19.143, v4.14.196, v4.9.235, v4.4.235. > > v5.8.7: Failed to apply! Possible dependencies: > 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout") > > v5.4.63: Failed to apply! Possible dependencies: > 268a2d600130 ("MIPS: Loongson64: Rename CPU TYPES") > 39b2d7565a47 ("MIPS: Kconfig: always select ARC_MEMORY and ARC_PROMLIB for platform") > 6fbde6b492df ("MIPS: Loongson64: Move files to the top-level directory") > 71e2f4dd5a65 ("MIPS: Fork loongson2ef from loongson64") > 7505576d1c1a ("MIPS: add support for SGI Octane (IP30)") > 863be3c3ab73 ("MIPS: Add header files reference with path prefix") > 8bec3875c547 ("MIPS: Loongson64: Drop legacy IRQ code") > 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout") > > v4.19.143: Failed to apply! Possible dependencies: > 05a0a3441869 ("rtc: mips: default to rtc-cmos on mips") > 69a07a41d908 ("MIPS: SGI-IP27: rework HUB interrupts") > 863be3c3ab73 ("MIPS: Add header files reference with path prefix") > 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout") > eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci") > > v4.14.196: Failed to apply! Possible dependencies: > 3d8757b87d7f ("s390/sthyi: add s390_sthyi system call") > 69a07a41d908 ("MIPS: SGI-IP27: rework HUB interrupts") > 71406883fd35 ("s390/kexec_file: Add kexec_file_load system call") > 840798a1f529 ("s390/kexec_file: Add purgatory") > 863be3c3ab73 ("MIPS: Add header files reference with path prefix") > 87a4c375995e ("kconfig: include kernel/Kconfig.preempt from init/Kconfig") > 8e6d08e0a15e ("openrisc: initial SMP support") > 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout") > 9fb6c9b3fea1 ("s390/sthyi: add cache to store hypervisor info") > b7c92f1a4e13 ("s390/sthyi: reorganize sthyi implementation") > c33eff600584 ("s390/perf: add perf_regs support and user stack dump") > e71ea3badae5 ("nds32: Build infrastructure") > eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci") > fbe934d69eb7 ("RISC-V: Build Infrastructure") > > v4.9.235: Failed to apply! Possible dependencies: > 043b42bcbbc6 ("arch/openrisc: add option to skip DMA sync as a part of mapping") > 07c75d7a6b9e ("drivers: dma-mapping: allow dma_common_mmap() for NOMMU") > 266c7fad1572 ("openrisc: Consolidate setup to use memblock instead of bootmem") > 34bbdcdcda88 ("openrisc: add NR_CPUS Kconfig default value") > 3e06a1633930 ("openrisc: add cache way information to cpuinfo") > 550116d21a65 ("scripts/spelling.txt: add "aligment" pattern and fix typo instances") > 63104c06a9ed ("openrisc: add l.lwa/l.swa emulation") > 69a07a41d908 ("MIPS: SGI-IP27: rework HUB interrupts") > 6d526ee26ccd ("arm64: mm: enable CONFIG_HOLES_IN_ZONE for NUMA") > 7844572c6339 ("lib/dma-noop: Only build dma_noop_ops for s390 and m32r") > 863be3c3ab73 ("MIPS: Add header files reference with path prefix") > 87a4c375995e ("kconfig: include kernel/Kconfig.preempt from init/Kconfig") > 8c9b7db0de3d ("openrisc: head: refactor out tlb flush into it's own function") > 8e6d08e0a15e ("openrisc: initial SMP support") > 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout") > da6b21e97e39 ("ARM: Drop fixed 200 Hz timer requirement from Samsung platforms") > e1231b0e487c ("s390: add cma support") > e71ea3badae5 ("nds32: Build infrastructure") > eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci") > > v4.4.235: Failed to apply! Possible dependencies: > 0d4a619b64ba ("dma-mapping: make the generic coherent dma mmap implementation optional") > 1a2db300348b ("arm64, numa: Add NUMA support for arm64 platforms.") > 37eda9df5bd8 ("ARC: mm: Introduce explicit super page size support") > 42b510eb56de ("h8300: Add LZO compression") > 69a07a41d908 ("MIPS: SGI-IP27: rework HUB interrupts") > 6d526ee26ccd ("arm64: mm: enable CONFIG_HOLES_IN_ZONE for NUMA") > 79387179e2e4 ("parisc: convert to dma_map_ops") > 7af3a0a99252 ("arm64/numa: support HAVE_SETUP_PER_CPU_AREA") > 863be3c3ab73 ("MIPS: Add header files reference with path prefix") > 87a4c375995e ("kconfig: include kernel/Kconfig.preempt from init/Kconfig") > 910cd32e552e ("parisc: Fix and enable seccomp filter support") > 925a567542c5 ("MIPS: Loongson64: Adjust IRQ layout") > 96ff2d7081cf ("h8300: Add KGDB support.") > 97a23beb8db9 ("clocksource/drivers/h8300_timer8: Separate the Kconfig option from the arch") > da6b21e97e39 ("ARM: Drop fixed 200 Hz timer requirement from Samsung platforms") > eb01d42a7778 ("PCI: consolidate PCI config entry in drivers/pci") > fff7fb0b2d90 ("lib/GCD.c: use binary GCD algorithm instead of Euclidean") > > > NOTE: The patch will not be queued to stable trees until it is upstream. > > How should we proceed with this patch? I'm sorry that this patch is only needed in 5.9+, please ignore my noise. Huacai > > -- > Thanks > Sasha
Hi, Marc, On Thu, Sep 10, 2020 at 6:10 PM Marc Zyngier <maz@kernel.org> wrote: > > On 2020-09-09 05:09, Huacai Chen wrote: > > Modernized Loongson64 uses a hierarchical organization for interrupt > > controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ > > numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) > > is not enough to represent all interrupts, so let's increase NR_IRQS to > > 320. > > > > Cc: stable@vger.kernel.org > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > > --- > > arch/mips/include/asm/mach-loongson64/irq.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/mips/include/asm/mach-loongson64/irq.h > > b/arch/mips/include/asm/mach-loongson64/irq.h > > index f5e362f7..0da3017 100644 > > --- a/arch/mips/include/asm/mach-loongson64/irq.h > > +++ b/arch/mips/include/asm/mach-loongson64/irq.h > > @@ -7,7 +7,7 @@ > > /* cpu core interrupt numbers */ > > #define NR_IRQS_LEGACY 16 > > #define NR_MIPS_CPU_IRQS 8 > > -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) > > +#define NR_IRQS 320 > > > > #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY > > Why are you hardcoding a random value instead of bumping the constant > in NR_IRQS? Because INTCs can organized in many kinds of hierarchy, we cannot use constants to define a accurate value, but 320 is big enough. Huacai > > M. > -- > Jazz is not dead. It just smells funny...
On 2020-09-11 04:24, Huacai Chen wrote: > Hi, Marc, > > On Thu, Sep 10, 2020 at 6:10 PM Marc Zyngier <maz@kernel.org> wrote: >> >> On 2020-09-09 05:09, Huacai Chen wrote: >> > Modernized Loongson64 uses a hierarchical organization for interrupt >> > controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ >> > numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) >> > is not enough to represent all interrupts, so let's increase NR_IRQS to >> > 320. >> > >> > Cc: stable@vger.kernel.org >> > Signed-off-by: Huacai Chen <chenhc@lemote.com> >> > --- >> > arch/mips/include/asm/mach-loongson64/irq.h | 2 +- >> > 1 file changed, 1 insertion(+), 1 deletion(-) >> > >> > diff --git a/arch/mips/include/asm/mach-loongson64/irq.h >> > b/arch/mips/include/asm/mach-loongson64/irq.h >> > index f5e362f7..0da3017 100644 >> > --- a/arch/mips/include/asm/mach-loongson64/irq.h >> > +++ b/arch/mips/include/asm/mach-loongson64/irq.h >> > @@ -7,7 +7,7 @@ >> > /* cpu core interrupt numbers */ >> > #define NR_IRQS_LEGACY 16 >> > #define NR_MIPS_CPU_IRQS 8 >> > -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) >> > +#define NR_IRQS 320 >> > >> > #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY >> >> Why are you hardcoding a random value instead of bumping the constant >> in NR_IRQS? > Because INTCs can organized in many kinds of hierarchy, we cannot use > constants to define a accurate value, but 320 is big enough. You're not answering my question. You have a parameterized NR_IRQS, and you're turning it into an absolute constant. Why? I.e: #define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 296) And why 320? Why not 512? or 2^15? As for a "modernized" setup, the fact that you are not using SPARSE_IRQ is pretty backward. M.
Hi, Marc, On Fri, Sep 11, 2020 at 3:45 PM Marc Zyngier <maz@kernel.org> wrote: > > On 2020-09-11 04:24, Huacai Chen wrote: > > Hi, Marc, > > > > On Thu, Sep 10, 2020 at 6:10 PM Marc Zyngier <maz@kernel.org> wrote: > >> > >> On 2020-09-09 05:09, Huacai Chen wrote: > >> > Modernized Loongson64 uses a hierarchical organization for interrupt > >> > controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ > >> > numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) > >> > is not enough to represent all interrupts, so let's increase NR_IRQS to > >> > 320. > >> > > >> > Cc: stable@vger.kernel.org > >> > Signed-off-by: Huacai Chen <chenhc@lemote.com> > >> > --- > >> > arch/mips/include/asm/mach-loongson64/irq.h | 2 +- > >> > 1 file changed, 1 insertion(+), 1 deletion(-) > >> > > >> > diff --git a/arch/mips/include/asm/mach-loongson64/irq.h > >> > b/arch/mips/include/asm/mach-loongson64/irq.h > >> > index f5e362f7..0da3017 100644 > >> > --- a/arch/mips/include/asm/mach-loongson64/irq.h > >> > +++ b/arch/mips/include/asm/mach-loongson64/irq.h > >> > @@ -7,7 +7,7 @@ > >> > /* cpu core interrupt numbers */ > >> > #define NR_IRQS_LEGACY 16 > >> > #define NR_MIPS_CPU_IRQS 8 > >> > -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) > >> > +#define NR_IRQS 320 > >> > > >> > #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY > >> > >> Why are you hardcoding a random value instead of bumping the constant > >> in NR_IRQS? > > Because INTCs can organized in many kinds of hierarchy, we cannot use > > constants to define a accurate value, but 320 is big enough. > > You're not answering my question. You have a parameterized NR_IRQS, and > you're turning it into an absolute constant. Why? I.e: > > #define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 296) > > And why 320? Why not 512? or 2^15? OK, I know, I will define a NR_MAX_MIDDLE_IRQS and then define NR_IRQS as (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_MIDDLE_IRQS + 256) > > As for a "modernized" setup, the fact that you are not using SPARSE_IRQ > is pretty backward. I have discussed this with Jiaxun, and he said that there are some difficulties to use SPARSE_IRQ. Huacai > > M. > -- > Jazz is not dead. It just smells funny...
On 2020-09-11 09:43, Huacai Chen wrote: > Hi, Marc, > > On Fri, Sep 11, 2020 at 3:45 PM Marc Zyngier <maz@kernel.org> wrote: >> >> On 2020-09-11 04:24, Huacai Chen wrote: >> > Hi, Marc, >> > >> > On Thu, Sep 10, 2020 at 6:10 PM Marc Zyngier <maz@kernel.org> wrote: >> >> >> >> On 2020-09-09 05:09, Huacai Chen wrote: >> >> > Modernized Loongson64 uses a hierarchical organization for interrupt >> >> > controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ >> >> > numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) >> >> > is not enough to represent all interrupts, so let's increase NR_IRQS to >> >> > 320. >> >> > >> >> > Cc: stable@vger.kernel.org >> >> > Signed-off-by: Huacai Chen <chenhc@lemote.com> >> >> > --- >> >> > arch/mips/include/asm/mach-loongson64/irq.h | 2 +- >> >> > 1 file changed, 1 insertion(+), 1 deletion(-) >> >> > >> >> > diff --git a/arch/mips/include/asm/mach-loongson64/irq.h >> >> > b/arch/mips/include/asm/mach-loongson64/irq.h >> >> > index f5e362f7..0da3017 100644 >> >> > --- a/arch/mips/include/asm/mach-loongson64/irq.h >> >> > +++ b/arch/mips/include/asm/mach-loongson64/irq.h >> >> > @@ -7,7 +7,7 @@ >> >> > /* cpu core interrupt numbers */ >> >> > #define NR_IRQS_LEGACY 16 >> >> > #define NR_MIPS_CPU_IRQS 8 >> >> > -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) >> >> > +#define NR_IRQS 320 >> >> > >> >> > #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY >> >> >> >> Why are you hardcoding a random value instead of bumping the constant >> >> in NR_IRQS? >> > Because INTCs can organized in many kinds of hierarchy, we cannot use >> > constants to define a accurate value, but 320 is big enough. >> >> You're not answering my question. You have a parameterized NR_IRQS, >> and >> you're turning it into an absolute constant. Why? I.e: >> >> #define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 296) >> >> And why 320? Why not 512? or 2^15? > OK, I know, I will define a NR_MAX_MIDDLE_IRQS and then define NR_IRQS > as (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_MIDDLE_IRQS + 256) What does MIDDLE_IRQS mean? Please name it to something that actually relates to its usage... >> >> As for a "modernized" setup, the fact that you are not using >> SPARSE_IRQ >> is pretty backward. > I have discussed this with Jiaxun, and he said that there are some > difficulties to use SPARSE_IRQ. It'd be worth considering putting some efforts there... M.
Hi, Marc, On Fri, Sep 11, 2020 at 5:03 PM Marc Zyngier <maz@kernel.org> wrote: > > On 2020-09-11 09:43, Huacai Chen wrote: > > Hi, Marc, > > > > On Fri, Sep 11, 2020 at 3:45 PM Marc Zyngier <maz@kernel.org> wrote: > >> > >> On 2020-09-11 04:24, Huacai Chen wrote: > >> > Hi, Marc, > >> > > >> > On Thu, Sep 10, 2020 at 6:10 PM Marc Zyngier <maz@kernel.org> wrote: > >> >> > >> >> On 2020-09-09 05:09, Huacai Chen wrote: > >> >> > Modernized Loongson64 uses a hierarchical organization for interrupt > >> >> > controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ > >> >> > numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) > >> >> > is not enough to represent all interrupts, so let's increase NR_IRQS to > >> >> > 320. > >> >> > > >> >> > Cc: stable@vger.kernel.org > >> >> > Signed-off-by: Huacai Chen <chenhc@lemote.com> > >> >> > --- > >> >> > arch/mips/include/asm/mach-loongson64/irq.h | 2 +- > >> >> > 1 file changed, 1 insertion(+), 1 deletion(-) > >> >> > > >> >> > diff --git a/arch/mips/include/asm/mach-loongson64/irq.h > >> >> > b/arch/mips/include/asm/mach-loongson64/irq.h > >> >> > index f5e362f7..0da3017 100644 > >> >> > --- a/arch/mips/include/asm/mach-loongson64/irq.h > >> >> > +++ b/arch/mips/include/asm/mach-loongson64/irq.h > >> >> > @@ -7,7 +7,7 @@ > >> >> > /* cpu core interrupt numbers */ > >> >> > #define NR_IRQS_LEGACY 16 > >> >> > #define NR_MIPS_CPU_IRQS 8 > >> >> > -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) > >> >> > +#define NR_IRQS 320 > >> >> > > >> >> > #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY > >> >> > >> >> Why are you hardcoding a random value instead of bumping the constant > >> >> in NR_IRQS? > >> > Because INTCs can organized in many kinds of hierarchy, we cannot use > >> > constants to define a accurate value, but 320 is big enough. > >> > >> You're not answering my question. You have a parameterized NR_IRQS, > >> and > >> you're turning it into an absolute constant. Why? I.e: > >> > >> #define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 296) > >> > >> And why 320? Why not 512? or 2^15? > > OK, I know, I will define a NR_MAX_MIDDLE_IRQS and then define NR_IRQS > > as (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_MIDDLE_IRQS + 256) > > What does MIDDLE_IRQS mean? Please name it to something that actually > relates to its usage... INTCs are organized as a tree, MIDDLE_IRQS means those IRQS used by middle nodes (not leaf nodes and not root node), midde nodes is not directed by devices, but they consumes irq numbers. > > >> > >> As for a "modernized" setup, the fact that you are not using > >> SPARSE_IRQ > >> is pretty backward. > > I have discussed this with Jiaxun, and he said that there are some > > difficulties to use SPARSE_IRQ. > > It'd be worth considering putting some efforts there... Yes, but that is another topic. Huacai > > M. > -- > Jazz is not dead. It just smells funny...
On 2020-09-11 10:14, Huacai Chen wrote: > Hi, Marc, > > On Fri, Sep 11, 2020 at 5:03 PM Marc Zyngier <maz@kernel.org> wrote: >> >> On 2020-09-11 09:43, Huacai Chen wrote: >> > Hi, Marc, >> > >> > On Fri, Sep 11, 2020 at 3:45 PM Marc Zyngier <maz@kernel.org> wrote: >> >> >> >> On 2020-09-11 04:24, Huacai Chen wrote: >> >> > Hi, Marc, >> >> > >> >> > On Thu, Sep 10, 2020 at 6:10 PM Marc Zyngier <maz@kernel.org> wrote: >> >> >> >> >> >> On 2020-09-09 05:09, Huacai Chen wrote: >> >> >> > Modernized Loongson64 uses a hierarchical organization for interrupt >> >> >> > controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ >> >> >> > numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) >> >> >> > is not enough to represent all interrupts, so let's increase NR_IRQS to >> >> >> > 320. >> >> >> > >> >> >> > Cc: stable@vger.kernel.org >> >> >> > Signed-off-by: Huacai Chen <chenhc@lemote.com> >> >> >> > --- >> >> >> > arch/mips/include/asm/mach-loongson64/irq.h | 2 +- >> >> >> > 1 file changed, 1 insertion(+), 1 deletion(-) >> >> >> > >> >> >> > diff --git a/arch/mips/include/asm/mach-loongson64/irq.h >> >> >> > b/arch/mips/include/asm/mach-loongson64/irq.h >> >> >> > index f5e362f7..0da3017 100644 >> >> >> > --- a/arch/mips/include/asm/mach-loongson64/irq.h >> >> >> > +++ b/arch/mips/include/asm/mach-loongson64/irq.h >> >> >> > @@ -7,7 +7,7 @@ >> >> >> > /* cpu core interrupt numbers */ >> >> >> > #define NR_IRQS_LEGACY 16 >> >> >> > #define NR_MIPS_CPU_IRQS 8 >> >> >> > -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) >> >> >> > +#define NR_IRQS 320 >> >> >> > >> >> >> > #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY >> >> >> >> >> >> Why are you hardcoding a random value instead of bumping the constant >> >> >> in NR_IRQS? >> >> > Because INTCs can organized in many kinds of hierarchy, we cannot use >> >> > constants to define a accurate value, but 320 is big enough. >> >> >> >> You're not answering my question. You have a parameterized NR_IRQS, >> >> and >> >> you're turning it into an absolute constant. Why? I.e: >> >> >> >> #define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 296) >> >> >> >> And why 320? Why not 512? or 2^15? >> > OK, I know, I will define a NR_MAX_MIDDLE_IRQS and then define NR_IRQS >> > as (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_MIDDLE_IRQS + 256) >> >> What does MIDDLE_IRQS mean? Please name it to something that actually >> relates to its usage... > INTCs are organized as a tree, MIDDLE_IRQS means those IRQS used by Tell me something I don't know... > middle nodes (not leaf nodes and not root node), midde nodes is not > directed by devices, but they consumes irq numbers. Then name the #define something that represents its use. "middle" doesn't describe anything. Call it "chained", or "cascade", or something at actually reflects the topology of these systems. > >> >> >> >> >> As for a "modernized" setup, the fact that you are not using >> >> SPARSE_IRQ >> >> is pretty backward. >> > I have discussed this with Jiaxun, and he said that there are some >> > difficulties to use SPARSE_IRQ. >> >> It'd be worth considering putting some efforts there... > Yes, but that is another topic. It really is the same topic. You keep bumping this NR_IRQS up in arbitrary ways, which would be avoided if you brought MIPS into the 21st century. M.
Hi, Marc, On Fri, Sep 11, 2020 at 5:23 PM Marc Zyngier <maz@kernel.org> wrote: > > On 2020-09-11 10:14, Huacai Chen wrote: > > Hi, Marc, > > > > On Fri, Sep 11, 2020 at 5:03 PM Marc Zyngier <maz@kernel.org> wrote: > >> > >> On 2020-09-11 09:43, Huacai Chen wrote: > >> > Hi, Marc, > >> > > >> > On Fri, Sep 11, 2020 at 3:45 PM Marc Zyngier <maz@kernel.org> wrote: > >> >> > >> >> On 2020-09-11 04:24, Huacai Chen wrote: > >> >> > Hi, Marc, > >> >> > > >> >> > On Thu, Sep 10, 2020 at 6:10 PM Marc Zyngier <maz@kernel.org> wrote: > >> >> >> > >> >> >> On 2020-09-09 05:09, Huacai Chen wrote: > >> >> >> > Modernized Loongson64 uses a hierarchical organization for interrupt > >> >> >> > controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ > >> >> >> > numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) > >> >> >> > is not enough to represent all interrupts, so let's increase NR_IRQS to > >> >> >> > 320. > >> >> >> > > >> >> >> > Cc: stable@vger.kernel.org > >> >> >> > Signed-off-by: Huacai Chen <chenhc@lemote.com> > >> >> >> > --- > >> >> >> > arch/mips/include/asm/mach-loongson64/irq.h | 2 +- > >> >> >> > 1 file changed, 1 insertion(+), 1 deletion(-) > >> >> >> > > >> >> >> > diff --git a/arch/mips/include/asm/mach-loongson64/irq.h > >> >> >> > b/arch/mips/include/asm/mach-loongson64/irq.h > >> >> >> > index f5e362f7..0da3017 100644 > >> >> >> > --- a/arch/mips/include/asm/mach-loongson64/irq.h > >> >> >> > +++ b/arch/mips/include/asm/mach-loongson64/irq.h > >> >> >> > @@ -7,7 +7,7 @@ > >> >> >> > /* cpu core interrupt numbers */ > >> >> >> > #define NR_IRQS_LEGACY 16 > >> >> >> > #define NR_MIPS_CPU_IRQS 8 > >> >> >> > -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) > >> >> >> > +#define NR_IRQS 320 > >> >> >> > > >> >> >> > #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY > >> >> >> > >> >> >> Why are you hardcoding a random value instead of bumping the constant > >> >> >> in NR_IRQS? > >> >> > Because INTCs can organized in many kinds of hierarchy, we cannot use > >> >> > constants to define a accurate value, but 320 is big enough. > >> >> > >> >> You're not answering my question. You have a parameterized NR_IRQS, > >> >> and > >> >> you're turning it into an absolute constant. Why? I.e: > >> >> > >> >> #define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 296) > >> >> > >> >> And why 320? Why not 512? or 2^15? > >> > OK, I know, I will define a NR_MAX_MIDDLE_IRQS and then define NR_IRQS > >> > as (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_MIDDLE_IRQS + 256) > >> > >> What does MIDDLE_IRQS mean? Please name it to something that actually > >> relates to its usage... > > INTCs are organized as a tree, MIDDLE_IRQS means those IRQS used by > > Tell me something I don't know... > > > middle nodes (not leaf nodes and not root node), midde nodes is not > > directed by devices, but they consumes irq numbers. > > Then name the #define something that represents its use. "middle" > doesn't > describe anything. Call it "chained", or "cascade", or something at > actually > reflects the topology of these systems. I choose "chained". > > > > >> > >> >> > >> >> As for a "modernized" setup, the fact that you are not using > >> >> SPARSE_IRQ > >> >> is pretty backward. > >> > I have discussed this with Jiaxun, and he said that there are some > >> > difficulties to use SPARSE_IRQ. > >> > >> It'd be worth considering putting some efforts there... > > Yes, but that is another topic. > > It really is the same topic. You keep bumping this NR_IRQS up in > arbitrary ways, > which would be avoided if you brought MIPS into the 21st century. Jiaxun, please explain why you don't use SPARSE_IRQ? Huacai > > M. > -- > Jazz is not dead. It just smells funny...
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index f5e362f7..0da3017 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -7,7 +7,7 @@ /* cpu core interrupt numbers */ #define NR_IRQS_LEGACY 16 #define NR_MIPS_CPU_IRQS 8 -#define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) +#define NR_IRQS 320 #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY
Modernized Loongson64 uses a hierarchical organization for interrupt controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256) is not enough to represent all interrupts, so let's increase NR_IRQS to 320. Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen <chenhc@lemote.com> --- arch/mips/include/asm/mach-loongson64/irq.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)