diff mbox series

[V9,3/4] drm/i915/dsi: Add TE handler for dsi cmd mode.

Message ID 20200909085047.31004-4-vandita.kulkarni@intel.com (mailing list archive)
State New, archived
Headers show
Series Add support for mipi dsi cmd mode | expand

Commit Message

Kulkarni, Vandita Sept. 9, 2020, 8:50 a.m. UTC
In case of dual link, we get the TE on slave.
So clear the TE on slave DSI IIR.

If we are operating in TE_GATE mode, after we do
a frame update, the transcoder will send the frame data
to the panel, after it receives a TE. Whereas if we
are operating in NO_GATE mode then the transcoder will
immediately send the frame data to the panel.
We are not dealing with the periodic command mode here.

v2: Pass only relevant masked bits to the handler (Jani)

v3: Fix the check for cmd mode in TE handler function.

v4: Use intel_handle_vblank instead of drm_handle_vblank (Jani)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 66 +++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

Comments

kernel test robot Sept. 9, 2020, 12:30 p.m. UTC | #1
Hi Vandita,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on v5.9-rc4 next-20200908]
[cannot apply to drm-intel/for-linux-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20200909-165807
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-s002-20200909 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce:
        # apt-get install sparse
        # sparse version: v0.6.2-191-g10164920-dirty
        # save the attached .config to linux build tree
        make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=i386 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/i915_irq.c:2302:6: warning: no previous prototype for 'gen11_dsi_te_interrupt_handler' [-Wmissing-prototypes]
    2302 | void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
         |      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

sparse warnings: (new ones prefixed by >>)

>> drivers/gpu/drm/i915/i915_irq.c:2302:6: sparse: sparse: symbol 'gen11_dsi_te_interrupt_handler' was not declared. Should it be static?

Please review and possibly fold the followup patch.

# https://github.com/0day-ci/linux/commit/3b071e8b378aa99a24cedbc6d3525a17f8e203e5
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20200909-165807
git checkout 3b071e8b378aa99a24cedbc6d3525a17f8e203e5
vim +/gen11_dsi_te_interrupt_handler +2302 drivers/gpu/drm/i915/i915_irq.c

  2301	
> 2302	void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
  2303					    u32 te_trigger)
  2304	{
  2305		enum pipe pipe = INVALID_PIPE;
  2306		enum transcoder dsi_trans;
  2307		enum port port;
  2308		u32 val, tmp;
  2309	
  2310		/*
  2311		 * Incase of dual link, TE comes from DSI_1
  2312		 * this is to check if dual link is enabled
  2313		 */
  2314		val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
  2315		val &= PORT_SYNC_MODE_ENABLE;
  2316	
  2317		/*
  2318		 * if dual link is enabled, then read DSI_0
  2319		 * transcoder registers
  2320		 */
  2321		port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
  2322							  PORT_A : PORT_B;
  2323		dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
  2324	
  2325		/* Check if DSI configured in command mode */
  2326		val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
  2327		val = val & OP_MODE_MASK;
  2328	
  2329		if ((val != CMD_MODE_NO_GATE) && (val != CMD_MODE_TE_GATE)) {
  2330			drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n");
  2331			return;
  2332		}
  2333	
  2334		/* Get PIPE for handling VBLANK event */
  2335		val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
  2336		switch (val & TRANS_DDI_EDP_INPUT_MASK) {
  2337		case TRANS_DDI_EDP_INPUT_A_ON:
  2338			pipe = PIPE_A;
  2339			break;
  2340		case TRANS_DDI_EDP_INPUT_B_ONOFF:
  2341			pipe = PIPE_B;
  2342			break;
  2343		case TRANS_DDI_EDP_INPUT_C_ONOFF:
  2344			pipe = PIPE_C;
  2345			break;
  2346		default:
  2347			drm_err(&dev_priv->drm, "Invalid PIPE\n");
  2348			return;
  2349		}
  2350	
  2351		intel_handle_vblank(dev_priv, pipe);
  2352	
  2353		/* clear TE in dsi IIR */
  2354		port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
  2355		tmp = I915_READ(DSI_INTR_IDENT_REG(port));
  2356		I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
  2357	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
Jani Nikula Sept. 15, 2020, 12:01 p.m. UTC | #2
On Wed, 09 Sep 2020, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> In case of dual link, we get the TE on slave.
> So clear the TE on slave DSI IIR.
>
> If we are operating in TE_GATE mode, after we do
> a frame update, the transcoder will send the frame data
> to the panel, after it receives a TE. Whereas if we
> are operating in NO_GATE mode then the transcoder will
> immediately send the frame data to the panel.
> We are not dealing with the periodic command mode here.
>
> v2: Pass only relevant masked bits to the handler (Jani)
>
> v3: Fix the check for cmd mode in TE handler function.
>
> v4: Use intel_handle_vblank instead of drm_handle_vblank (Jani)
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 66 +++++++++++++++++++++++++++++++++
>  1 file changed, 66 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index de540194ce67..f8398c5cbd4a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2299,6 +2299,64 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
>  		drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
>  }
>  
> +void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,

Should be static.

Otherwise,

Acked-by: Jani Nikula <jani.nikula@intel.com>


> +				    u32 te_trigger)
> +{
> +	enum pipe pipe = INVALID_PIPE;
> +	enum transcoder dsi_trans;
> +	enum port port;
> +	u32 val, tmp;
> +
> +	/*
> +	 * Incase of dual link, TE comes from DSI_1
> +	 * this is to check if dual link is enabled
> +	 */
> +	val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
> +	val &= PORT_SYNC_MODE_ENABLE;
> +
> +	/*
> +	 * if dual link is enabled, then read DSI_0
> +	 * transcoder registers
> +	 */
> +	port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
> +						  PORT_A : PORT_B;
> +	dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
> +
> +	/* Check if DSI configured in command mode */
> +	val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
> +	val = val & OP_MODE_MASK;
> +
> +	if ((val != CMD_MODE_NO_GATE) && (val != CMD_MODE_TE_GATE)) {
> +		drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n");
> +		return;
> +	}
> +
> +	/* Get PIPE for handling VBLANK event */
> +	val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
> +	switch (val & TRANS_DDI_EDP_INPUT_MASK) {
> +	case TRANS_DDI_EDP_INPUT_A_ON:
> +		pipe = PIPE_A;
> +		break;
> +	case TRANS_DDI_EDP_INPUT_B_ONOFF:
> +		pipe = PIPE_B;
> +		break;
> +	case TRANS_DDI_EDP_INPUT_C_ONOFF:
> +		pipe = PIPE_C;
> +		break;
> +	default:
> +		drm_err(&dev_priv->drm, "Invalid PIPE\n");
> +		return;
> +	}
> +
> +	intel_handle_vblank(dev_priv, pipe);
> +
> +	/* clear TE in dsi IIR */
> +	port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
> +	tmp = I915_READ(DSI_INTR_IDENT_REG(port));
> +	I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
> +
> +}
> +
>  static irqreturn_t
>  gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>  {
> @@ -2363,6 +2421,14 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>  				found = true;
>  			}
>  
> +			if (INTEL_GEN(dev_priv) >= 11) {
> +				tmp_mask = iir & (DSI0_TE | DSI1_TE);
> +				if (tmp_mask) {
> +					gen11_dsi_te_interrupt_handler(dev_priv, tmp_mask);
> +					found = true;
> +				}
> +			}
> +
>  			if (!found)
>  				drm_err(&dev_priv->drm,
>  					"Unexpected DE Port interrupt\n");
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index de540194ce67..f8398c5cbd4a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2299,6 +2299,64 @@  gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
 		drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
 }
 
+void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv,
+				    u32 te_trigger)
+{
+	enum pipe pipe = INVALID_PIPE;
+	enum transcoder dsi_trans;
+	enum port port;
+	u32 val, tmp;
+
+	/*
+	 * Incase of dual link, TE comes from DSI_1
+	 * this is to check if dual link is enabled
+	 */
+	val = I915_READ(TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0));
+	val &= PORT_SYNC_MODE_ENABLE;
+
+	/*
+	 * if dual link is enabled, then read DSI_0
+	 * transcoder registers
+	 */
+	port = ((te_trigger & DSI1_TE && val) || (te_trigger & DSI0_TE)) ?
+						  PORT_A : PORT_B;
+	dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1;
+
+	/* Check if DSI configured in command mode */
+	val = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
+	val = val & OP_MODE_MASK;
+
+	if ((val != CMD_MODE_NO_GATE) && (val != CMD_MODE_TE_GATE)) {
+		drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n");
+		return;
+	}
+
+	/* Get PIPE for handling VBLANK event */
+	val = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
+	switch (val & TRANS_DDI_EDP_INPUT_MASK) {
+	case TRANS_DDI_EDP_INPUT_A_ON:
+		pipe = PIPE_A;
+		break;
+	case TRANS_DDI_EDP_INPUT_B_ONOFF:
+		pipe = PIPE_B;
+		break;
+	case TRANS_DDI_EDP_INPUT_C_ONOFF:
+		pipe = PIPE_C;
+		break;
+	default:
+		drm_err(&dev_priv->drm, "Invalid PIPE\n");
+		return;
+	}
+
+	intel_handle_vblank(dev_priv, pipe);
+
+	/* clear TE in dsi IIR */
+	port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A;
+	tmp = I915_READ(DSI_INTR_IDENT_REG(port));
+	I915_WRITE(DSI_INTR_IDENT_REG(port), tmp);
+
+}
+
 static irqreturn_t
 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 {
@@ -2363,6 +2421,14 @@  gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 				found = true;
 			}
 
+			if (INTEL_GEN(dev_priv) >= 11) {
+				tmp_mask = iir & (DSI0_TE | DSI1_TE);
+				if (tmp_mask) {
+					gen11_dsi_te_interrupt_handler(dev_priv, tmp_mask);
+					found = true;
+				}
+			}
+
 			if (!found)
 				drm_err(&dev_priv->drm,
 					"Unexpected DE Port interrupt\n");