| Message ID | 1600052684-21198-2-git-send-email-henryc.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add driver for dvfsrc, support for active state of scpsys | expand |
On Mon, Sep 14, 2020 at 11:04:28AM +0800, Henry Chen wrote: > Document the binding for enabling dvfsrc on MediaTek SoC. > > Signed-off-by: Henry Chen <henryc.chen@mediatek.com> > Reviewed-by: Rob Herring <robh@kernel.org> I did, but bindings are in DT schema format now. We had a grace period for some time, but please convert this to DT schema. Rob > --- > .../devicetree/bindings/soc/mediatek/dvfsrc.txt | 25 ++++++++++++++++++++++ > include/dt-bindings/soc/mtk,dvfsrc.h | 14 ++++++++++++ > 2 files changed, 39 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt > create mode 100644 include/dt-bindings/soc/mtk,dvfsrc.h > > diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt > new file mode 100644 > index 0000000..d5a47d8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt > @@ -0,0 +1,25 @@ > +MediaTek DVFSRC > + > +The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a > +HW module which is used to collect all the requests from both software and > +hardware and turn into the decision of minimum operating voltage and minimum > +DRAM frequency to fulfill those requests. > + > +Required Properties: > +- compatible: Should be one of the following > + - "mediatek,mt6873-dvfsrc": For MT6873 SoC > + - "mediatek,mt8183-dvfsrc": For MT8183 SoC > + - "mediatek,mt8192-dvfsrc": For MT8192 SoC > +- reg: Address range of the DVFSRC unit > +- clock-names: Must include the following entries: > + "dvfsrc": DVFSRC module clock > +- clocks: Must contain an entry for each entry in clock-names. > + > +Example: > + > + dvfsrc@10012000 { > + compatible = "mediatek,mt8183-dvfsrc"; > + reg = <0 0x10012000 0 0x1000>; > + clocks = <&infracfg CLK_INFRA_DVFSRC>; > + clock-names = "dvfsrc"; > + }; > diff --git a/include/dt-bindings/soc/mtk,dvfsrc.h b/include/dt-bindings/soc/mtk,dvfsrc.h > new file mode 100644 > index 0000000..a522488 > --- /dev/null > +++ b/include/dt-bindings/soc/mtk,dvfsrc.h > @@ -0,0 +1,14 @@ > +/* SPDX-License-Identifier: GPL-2.0 > + * > + * Copyright (c) 2018 MediaTek Inc. > + */ > + > +#ifndef _DT_BINDINGS_POWER_MTK_DVFSRC_H > +#define _DT_BINDINGS_POWER_MTK_DVFSRC_H > + > +#define MT8183_DVFSRC_LEVEL_1 1 > +#define MT8183_DVFSRC_LEVEL_2 2 > +#define MT8183_DVFSRC_LEVEL_3 3 > +#define MT8183_DVFSRC_LEVEL_4 4 > + > +#endif /* _DT_BINDINGS_POWER_MTK_DVFSRC_H */ > -- > 1.9.1
diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt new file mode 100644 index 0000000..d5a47d8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt @@ -0,0 +1,25 @@ +MediaTek DVFSRC + +The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a +HW module which is used to collect all the requests from both software and +hardware and turn into the decision of minimum operating voltage and minimum +DRAM frequency to fulfill those requests. + +Required Properties: +- compatible: Should be one of the following + - "mediatek,mt6873-dvfsrc": For MT6873 SoC + - "mediatek,mt8183-dvfsrc": For MT8183 SoC + - "mediatek,mt8192-dvfsrc": For MT8192 SoC +- reg: Address range of the DVFSRC unit +- clock-names: Must include the following entries: + "dvfsrc": DVFSRC module clock +- clocks: Must contain an entry for each entry in clock-names. + +Example: + + dvfsrc@10012000 { + compatible = "mediatek,mt8183-dvfsrc"; + reg = <0 0x10012000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_DVFSRC>; + clock-names = "dvfsrc"; + }; diff --git a/include/dt-bindings/soc/mtk,dvfsrc.h b/include/dt-bindings/soc/mtk,dvfsrc.h new file mode 100644 index 0000000..a522488 --- /dev/null +++ b/include/dt-bindings/soc/mtk,dvfsrc.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2018 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MTK_DVFSRC_H +#define _DT_BINDINGS_POWER_MTK_DVFSRC_H + +#define MT8183_DVFSRC_LEVEL_1 1 +#define MT8183_DVFSRC_LEVEL_2 2 +#define MT8183_DVFSRC_LEVEL_3 3 +#define MT8183_DVFSRC_LEVEL_4 4 + +#endif /* _DT_BINDINGS_POWER_MTK_DVFSRC_H */