| Message ID | 20200916132000.1850-5-manivannan.sadhasivam@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add PCIe support for SM8250 SoC | expand |
On Wed, Sep 16, 2020 at 06:49:59PM +0530, Manivannan Sadhasivam wrote: > The PCIe IP on SM8250 SoC is similar to the one used on SDM845. Hence > the support is added reusing the 2.7.0 ops. Only difference is the need > of ATU base, which will be fetched opionally if provided by DT/ACPI. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> s/opionally/optionally/ $ git log --oneline drivers/pci/controller/dwc/pcie-qcom.c | head -10 824001cb64c0 PCI: qcom: Replace define with standard value 51ed2c2b6026 PCI: qcom: Support pci speed set for ipq806x 8df093fe2ae1 PCI: qcom: Add ipq8064 rev2 variant de3c4bf64897 PCI: qcom: Add support for tx term offset for rev 2.1.0 5149901e9e6d PCI: qcom: Define some PARF params needed for ipq8064 SoC 6a114526af46 PCI: qcom: Use bulk clk api and assert on error ee367e2cdd22 PCI: qcom: Add missing reset for ipq806x dd58318c019f PCI: qcom: Change duplicate PCI reset to phy reset Make yours match, maybe like this: PCI: qcom: Add SM8250 SoC support That way the important information ("SM8250") isn't way at the end where it may get chopped off. If you're ambitious, do this for the non-PCI patches, too.
On Wed, Sep 16, 2020 at 06:49:59PM +0530, Manivannan Sadhasivam wrote: > The PCIe IP on SM8250 SoC is similar to the one used on SDM845. Hence > the support is added reusing the 2.7.0 ops. Only difference is the need > of ATU base, which will be fetched opionally if provided by DT/ACPI. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > drivers/pci/controller/dwc/pcie-qcom.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 3aac77a295ba..ca8ad354e09d 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1370,6 +1370,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) > struct pcie_port *pp; > struct dw_pcie *pci; > struct qcom_pcie *pcie; > + void __iomem *atu_base; > int ret; > > pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); > @@ -1422,6 +1423,11 @@ static int qcom_pcie_probe(struct platform_device *pdev) > goto err_pm_runtime_put; > } > > + /* Get the optional ATU region if provided */ > + atu_base = devm_platform_ioremap_resource_byname(pdev, "atu"); > + if (!IS_ERR(atu_base)) > + pci->atu_base = atu_base; > + This is getting moved to the DWC common code[1]. Rob [1] https://lore.kernel.org/r/1599814203-14441-3-git-send-email-hayashi.kunihiko@socionext.com > pcie->phy = devm_phy_optional_get(dev, "pciephy"); > if (IS_ERR(pcie->phy)) { > ret = PTR_ERR(pcie->phy); > @@ -1476,6 +1482,7 @@ static const struct of_device_id qcom_pcie_match[] = { > { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 }, > { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, > { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, > + { .compatible = "qcom,pcie-sm8250", .data = &ops_2_7_0 }, > { } > }; > > -- > 2.17.1 >
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 3aac77a295ba..ca8ad354e09d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1370,6 +1370,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) struct pcie_port *pp; struct dw_pcie *pci; struct qcom_pcie *pcie; + void __iomem *atu_base; int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); @@ -1422,6 +1423,11 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } + /* Get the optional ATU region if provided */ + atu_base = devm_platform_ioremap_resource_byname(pdev, "atu"); + if (!IS_ERR(atu_base)) + pci->atu_base = atu_base; + pcie->phy = devm_phy_optional_get(dev, "pciephy"); if (IS_ERR(pcie->phy)) { ret = PTR_ERR(pcie->phy); @@ -1476,6 +1482,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, + { .compatible = "qcom,pcie-sm8250", .data = &ops_2_7_0 }, { } };
The PCIe IP on SM8250 SoC is similar to the one used on SDM845. Hence the support is added reusing the 2.7.0 ops. Only difference is the need of ATU base, which will be fetched opionally if provided by DT/ACPI. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/pci/controller/dwc/pcie-qcom.c | 7 +++++++ 1 file changed, 7 insertions(+)