Message ID | 20200930020902.7522-1-yifeng.zhao@rock-chips.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add Rockchip NFC drivers for RK3308 and others | expand |
On 2020/9/30 上午10:08, Yifeng Zhao wrote: > Add NAND FLASH Controller(NFC) node for PX30 SoC. > > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> > --- > > Changes in v10: None > Changes in v9: None > Changes in v8: None > Changes in v7: None > Changes in v6: None > Changes in v5: None > Changes in v4: None > Changes in v3: None > Changes in v2: None > > arch/arm64/boot/dts/rockchip/px30.dtsi | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) Looks good to me, Reviewed-by: Kever Yang<kever.yang@rock-chips.com> Thanks, - Kever > > diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi > index 2695ea8cda14..6cd67e80d623 100644 > --- a/arch/arm64/boot/dts/rockchip/px30.dtsi > +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi > @@ -973,6 +973,21 @@ > status = "disabled"; > }; > > + nfc: nand-controller@ff3b0000 { > + compatible = "rockchip,px30-nfc"; > + reg = <0x0 0xff3b0000 0x0 0x4000>; > + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; > + clock-names = "ahb", "nfc"; > + assigned-clocks = <&cru SCLK_NANDC>; > + assigned-clock-rates = <150000000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 > + &flash_rdn &flash_rdy &flash_wrn &flash_dqs>; > + power-domains = <&power PX30_PD_MMC_NAND>; > + status = "disabled"; > + }; > + > gpu: gpu@ff400000 { > compatible = "rockchip,px30-mali", "arm,mali-bifrost"; > reg = <0x0 0xff400000 0x0 0x4000>;
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 2695ea8cda14..6cd67e80d623 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -973,6 +973,21 @@ status = "disabled"; }; + nfc: nand-controller@ff3b0000 { + compatible = "rockchip,px30-nfc"; + reg = <0x0 0xff3b0000 0x0 0x4000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; + clock-names = "ahb", "nfc"; + assigned-clocks = <&cru SCLK_NANDC>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 + &flash_rdn &flash_rdy &flash_wrn &flash_dqs>; + power-domains = <&power PX30_PD_MMC_NAND>; + status = "disabled"; + }; + gpu: gpu@ff400000 { compatible = "rockchip,px30-mali", "arm,mali-bifrost"; reg = <0x0 0xff400000 0x0 0x4000>;
Add NAND FLASH Controller(NFC) node for PX30 SoC. Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> --- Changes in v10: None Changes in v9: None Changes in v8: None Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/arm64/boot/dts/rockchip/px30.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+)