| Message ID | 1602558169-23140-1-git-send-email-igor.druzhinin@citrix.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/2] x86/intel: insert Ice Lake X (server) model numbers | expand |
On 13.10.2020 05:02, Igor Druzhinin wrote: > LBR, C-state MSRs and if_pschange_mc erratum applicability should correspond > to Ice Lake desktop according to External Design Specification vol.2. Could you tell me where this is publicly available? Even after spending quite a bit of time on searching for it, I can't seem to be able to find it. And the SDM doesn't have enough information (yet). > --- a/xen/arch/x86/acpi/cpu_idle.c > +++ b/xen/arch/x86/acpi/cpu_idle.c > @@ -183,6 +183,7 @@ static void do_get_hw_residencies(void *arg) > /* Ice Lake */ > case 0x7D: > case 0x7E: > + case 0x6A: > /* Kaby Lake */ > case 0x8E: > case 0x9E: Here and below please honor the (partial) sorting that's in effect. Jan
On 14/10/2020 16:47, Jan Beulich wrote: > On 13.10.2020 05:02, Igor Druzhinin wrote: >> LBR, C-state MSRs and if_pschange_mc erratum applicability should correspond >> to Ice Lake desktop according to External Design Specification vol.2. > > Could you tell me where this is publicly available? Even after spending > quite a bit of time on searching for it, I can't seem to be able to > find it. And the SDM doesn't have enough information (yet). True that SDM doesn't have this data. As I mentioned that data is taken from External Design Specification for Ice Lake server which is accessed using Intel account. I'm not completely sure it is right to make changes in open source project like Linux or Xen based on information which is not publicly available yet. But Intel is frequently doing this with Linux : even my second patch uses data taken from one of these documents and was committed by Intel to Linux first. Do we need the information publicly available to commit these changes as well? If not, we can run with these changes in our patchqueue until it gets out properly. Igor
On 14.10.2020 18:42, Igor Druzhinin wrote: > On 14/10/2020 16:47, Jan Beulich wrote: >> On 13.10.2020 05:02, Igor Druzhinin wrote: >>> LBR, C-state MSRs and if_pschange_mc erratum applicability should correspond >>> to Ice Lake desktop according to External Design Specification vol.2. >> >> Could you tell me where this is publicly available? Even after spending >> quite a bit of time on searching for it, I can't seem to be able to >> find it. And the SDM doesn't have enough information (yet). > > True that SDM doesn't have this data. As I mentioned that data is taken from > External Design Specification for Ice Lake server which is accessed using Intel > account. I'm not completely sure it is right to make changes in open source > project like Linux or Xen based on information which is not publicly available > yet. But Intel is frequently doing this with Linux : even my second patch uses > data taken from one of these documents and was committed by Intel to Linux first. > > Do we need the information publicly available to commit these changes as well? Not necessarily, but it means this patch needs to be acked by someone having access to the doc, which hence isn't me. Given the last SDM update was in May, I'm expecting a refresh any day now. Iirc updates where frequently done on a roughly quarterly basis. > If not, we can run with these changes in our patchqueue until it gets out properly. Well, I'm all for having such changes upstream as early as possible. Jan
diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index 27e0b52..7ad726a 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -183,6 +183,7 @@ static void do_get_hw_residencies(void *arg) /* Ice Lake */ case 0x7D: case 0x7E: + case 0x6A: /* Kaby Lake */ case 0x8E: case 0x9E: diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 86b8916..bce8b99 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2429,6 +2429,7 @@ static bool __init has_if_pschange_mc(void) case 0x55: /* Skylake-X / Cascade Lake */ case 0x7d: /* Ice Lake */ case 0x7e: /* Ice Lake */ + case 0x6a: /* Ice Lake-X */ case 0x8e: /* Kaby / Coffee / Whiskey Lake M */ case 0x9e: /* Kaby / Coffee / Whiskey Lake D */ case 0xa5: /* Comet Lake H/S */ @@ -2775,7 +2776,7 @@ static const struct lbr_info *last_branch_msr_get(void) /* Goldmont Plus */ case 0x7a: /* Ice Lake */ - case 0x7d: case 0x7e: + case 0x7d: case 0x7e: case 0x6a: /* Tremont */ case 0x86: /* Kaby Lake */
LBR, C-state MSRs and if_pschange_mc erratum applicability should correspond to Ice Lake desktop according to External Design Specification vol.2. Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com> --- xen/arch/x86/acpi/cpu_idle.c | 1 + xen/arch/x86/hvm/vmx/vmx.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-)