| Message ID | 20201015105259.27934-5-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for DP-HDMI2.1 PCON | expand |
> -----Original Message----- > From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com> > Sent: Thursday, October 15, 2020 4:23 PM > To: intel-gfx@lists.freedesktop.org > Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>; > Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com; > Sharma, Swati2 <swati2.sharma@intel.com> > Subject: [RFC 04/13] drm/i915: Capture max frl rate for PCON in dfp cap structure > > HDMI2.1 PCON advertises Max FRL bandwidth supported by the PCON and by the > sink. > > This patch captures these in dfp cap structure in intel_dp and uses these to > prune connector modes that cannot be supported by the PCON and sink FRL > bandwidth. > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > .../drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++++++++++++-- > 2 files changed, 32 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 0b5df8e44966..e2f58d0575a2 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1398,6 +1398,7 @@ struct intel_dp { > struct { > int min_tmds_clock, max_tmds_clock; > int max_dotclock; > + int pcon_max_frl, sink_max_frl; Append it with bw or rate. > u8 max_bpc; > bool ycbcr_444_to_420; > } dfp; > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 0902a9aeeda1..cd6934f28f32 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -683,6 +683,24 @@ intel_dp_mode_valid_downstream(struct > intel_connector *connector, > const struct drm_display_info *info = &connector->base.display_info; > int tmds_clock; > > + /* If PCON and HDMI2.1 sink both support FRL MODE, check FRL Use multi line comment style. > + * bandwidth constraints. > + */ > + if (intel_dp->dfp.pcon_max_frl) { > + int target_bw; > + int max_frl_bw; > + int bpp = intel_dp_mode_min_output_bpp(&connector->base, > mode); > + > + target_bw = bpp * DIV_ROUND_UP(target_clock, 1000000); To avoid any roundup errors, it would be good to multiple max_frl_bw by 1000000 than dividing target_clock > + > + max_frl_bw = min(intel_dp->dfp.pcon_max_frl, > + intel_dp->dfp.sink_max_frl); > + if (target_bw > max_frl_bw) > + return MODE_CLOCK_HIGH; > + > + return MODE_OK; > + } > + > if (intel_dp->dfp.max_dotclock && > target_clock > intel_dp->dfp.max_dotclock) > return MODE_CLOCK_HIGH; > @@ -6383,13 +6401,21 @@ intel_dp_update_dfp(struct intel_dp *intel_dp, > intel_dp->downstream_ports, > edid); > > + intel_dp->dfp.pcon_max_frl = > + drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, > + intel_dp->downstream_ports); > + > + intel_dp->dfp.sink_max_frl = > +drm_dp_get_hdmi_max_frl_bw(&intel_dp->aux); > + > drm_dbg_kms(&i915->drm, > - "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, > TMDS clock %d-%d\n", > + "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, > TMDS clock > +%d-%d, PCON Max FRL BW %dGbps, Sink Max FRL BW %dGbps\n", > connector->base.base.id, connector->base.name, > intel_dp->dfp.max_bpc, > intel_dp->dfp.max_dotclock, > intel_dp->dfp.min_tmds_clock, > - intel_dp->dfp.max_tmds_clock); > + intel_dp->dfp.max_tmds_clock, > + intel_dp->dfp.pcon_max_frl, > + intel_dp->dfp.sink_max_frl); > } > > static void > @@ -6479,6 +6505,9 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) > intel_dp->dfp.min_tmds_clock = 0; > intel_dp->dfp.max_tmds_clock = 0; > > + intel_dp->dfp.pcon_max_frl = 0; > + intel_dp->dfp.sink_max_frl = 0; > + > intel_dp->dfp.ycbcr_444_to_420 = false; > connector->base.ycbcr_420_allowed = false; } > -- > 2.17.1
On 10/19/2020 3:11 AM, Shankar, Uma wrote: > >> -----Original Message----- >> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com> >> Sent: Thursday, October 15, 2020 4:23 PM >> To: intel-gfx@lists.freedesktop.org >> Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>; >> Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com; >> Sharma, Swati2 <swati2.sharma@intel.com> >> Subject: [RFC 04/13] drm/i915: Capture max frl rate for PCON in dfp cap structure >> >> HDMI2.1 PCON advertises Max FRL bandwidth supported by the PCON and by the >> sink. >> >> This patch captures these in dfp cap structure in intel_dp and uses these to >> prune connector modes that cannot be supported by the PCON and sink FRL >> bandwidth. >> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> >> --- >> .../drm/i915/display/intel_display_types.h | 1 + >> drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++++++++++++-- >> 2 files changed, 32 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h >> b/drivers/gpu/drm/i915/display/intel_display_types.h >> index 0b5df8e44966..e2f58d0575a2 100644 >> --- a/drivers/gpu/drm/i915/display/intel_display_types.h >> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h >> @@ -1398,6 +1398,7 @@ struct intel_dp { >> struct { >> int min_tmds_clock, max_tmds_clock; >> int max_dotclock; >> +int pcon_max_frl, sink_max_frl; > Append it with bw or rate. Agreed, will add 'bw' for clarity. > >> u8 max_bpc; >> bool ycbcr_444_to_420; >> } dfp; >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c >> b/drivers/gpu/drm/i915/display/intel_dp.c >> index 0902a9aeeda1..cd6934f28f32 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dp.c >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c >> @@ -683,6 +683,24 @@ intel_dp_mode_valid_downstream(struct >> intel_connector *connector, >> const struct drm_display_info *info = &connector->base.display_info; >> int tmds_clock; >> >> +/* If PCON and HDMI2.1 sink both support FRL MODE, check FRL > Use multi line comment style. Agreed. Will take care in next version. > >> + * bandwidth constraints. >> + */ >> +if (intel_dp->dfp.pcon_max_frl) { >> +int target_bw; >> +int max_frl_bw; >> +int bpp = intel_dp_mode_min_output_bpp(&connector->base, >> mode); >> + >> +target_bw = bpp * DIV_ROUND_UP(target_clock, 1000000); > To avoid any roundup errors, it would be good to multiple max_frl_bw by 1000000 than dividing target_clock Alright. Will take care of this in next version. Thanks & Regards, Ankit > >> + >> +max_frl_bw = min(intel_dp->dfp.pcon_max_frl, >> + intel_dp->dfp.sink_max_frl); >> +if (target_bw > max_frl_bw) >> +return MODE_CLOCK_HIGH; >> + >> +return MODE_OK; >> +} >> + >> if (intel_dp->dfp.max_dotclock && >> target_clock > intel_dp->dfp.max_dotclock) >> return MODE_CLOCK_HIGH; >> @@ -6383,13 +6401,21 @@ intel_dp_update_dfp(struct intel_dp *intel_dp, >> intel_dp->downstream_ports, >> edid); >> >> +intel_dp->dfp.pcon_max_frl = >> +drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, >> + intel_dp->downstream_ports); >> + >> +intel_dp->dfp.sink_max_frl = >> +drm_dp_get_hdmi_max_frl_bw(&intel_dp->aux); >> + >> drm_dbg_kms(&i915->drm, >> - "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, >> TMDS clock %d-%d\n", >> + "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, >> TMDS clock >> +%d-%d, PCON Max FRL BW %dGbps, Sink Max FRL BW %dGbps\n", >> connector->base.base.id, connector->base.name, >> intel_dp->dfp.max_bpc, >> intel_dp->dfp.max_dotclock, >> intel_dp->dfp.min_tmds_clock, >> - intel_dp->dfp.max_tmds_clock); >> + intel_dp->dfp.max_tmds_clock, >> + intel_dp->dfp.pcon_max_frl, >> + intel_dp->dfp.sink_max_frl); >> } >> >> static void >> @@ -6479,6 +6505,9 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) >> intel_dp->dfp.min_tmds_clock = 0; >> intel_dp->dfp.max_tmds_clock = 0; >> >> +intel_dp->dfp.pcon_max_frl = 0; >> +intel_dp->dfp.sink_max_frl = 0; >> + >> intel_dp->dfp.ycbcr_444_to_420 = false; >> connector->base.ycbcr_420_allowed = false; } >> -- >> 2.17.1
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 0b5df8e44966..e2f58d0575a2 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1398,6 +1398,7 @@ struct intel_dp { struct { int min_tmds_clock, max_tmds_clock; int max_dotclock; + int pcon_max_frl, sink_max_frl; u8 max_bpc; bool ycbcr_444_to_420; } dfp; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0902a9aeeda1..cd6934f28f32 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -683,6 +683,24 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_info *info = &connector->base.display_info; int tmds_clock; + /* If PCON and HDMI2.1 sink both support FRL MODE, check FRL + * bandwidth constraints. + */ + if (intel_dp->dfp.pcon_max_frl) { + int target_bw; + int max_frl_bw; + int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode); + + target_bw = bpp * DIV_ROUND_UP(target_clock, 1000000); + + max_frl_bw = min(intel_dp->dfp.pcon_max_frl, + intel_dp->dfp.sink_max_frl); + if (target_bw > max_frl_bw) + return MODE_CLOCK_HIGH; + + return MODE_OK; + } + if (intel_dp->dfp.max_dotclock && target_clock > intel_dp->dfp.max_dotclock) return MODE_CLOCK_HIGH; @@ -6383,13 +6401,21 @@ intel_dp_update_dfp(struct intel_dp *intel_dp, intel_dp->downstream_ports, edid); + intel_dp->dfp.pcon_max_frl = + drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, + intel_dp->downstream_ports); + + intel_dp->dfp.sink_max_frl = drm_dp_get_hdmi_max_frl_bw(&intel_dp->aux); + drm_dbg_kms(&i915->drm, - "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d\n", + "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps, Sink Max FRL BW %dGbps\n", connector->base.base.id, connector->base.name, intel_dp->dfp.max_bpc, intel_dp->dfp.max_dotclock, intel_dp->dfp.min_tmds_clock, - intel_dp->dfp.max_tmds_clock); + intel_dp->dfp.max_tmds_clock, + intel_dp->dfp.pcon_max_frl, + intel_dp->dfp.sink_max_frl); } static void @@ -6479,6 +6505,9 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) intel_dp->dfp.min_tmds_clock = 0; intel_dp->dfp.max_tmds_clock = 0; + intel_dp->dfp.pcon_max_frl = 0; + intel_dp->dfp.sink_max_frl = 0; + intel_dp->dfp.ycbcr_444_to_420 = false; connector->base.ycbcr_420_allowed = false; }
HDMI2.1 PCON advertises Max FRL bandwidth supported by the PCON and by the sink. This patch captures these in dfp cap structure in intel_dp and uses these to prune connector modes that cannot be supported by the PCON and sink FRL bandwidth. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++++++++++++-- 2 files changed, 32 insertions(+), 2 deletions(-)