[2/6] Documetation: dt-bindings: add the samsung,exynos-pcie binding

Commit Message

Marek Szyprowski Oct. 19, 2020, 9:47 a.m. UTC

From: Jaehoon Chung <[e-mail]>

Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433
variant).

Signed-off-by: Jaehoon Chung <[e-mail]>
[mszyprow: updated the binding to latest driver changes, rewrote it in yaml,
	   rewrote commit message]
Signed-off-by: Marek Szyprowski <[e-mail]>
---
 .../bindings/pci/samsung,exynos-pcie.yaml     | 106 ++++++++++++++++++
 1 file changed, 106 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml

Comments

Krzysztof Kozlowski Oct. 19, 2020, 10:12 a.m. UTC | #1

On Mon, Oct 19, 2020 at 11:47:11AM +0200, Marek Szyprowski wrote:
> From: Jaehoon Chung <[e-mail]>
> 
> Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433
> variant).

The title has typo and actually entire "Doc" should be dropped. Just
"dt-bindings: pci:".  This applies to all DT patches.

> 
> Signed-off-by: Jaehoon Chung <[e-mail]>
> [mszyprow: updated the binding to latest driver changes, rewrote it in yaml,
> 	   rewrote commit message]

If you wrote them in YAML it should be a new patch of yours. It is the
same then as converting TXT to YAML.

> Signed-off-by: Marek Szyprowski <[e-mail]>
> ---
>  .../bindings/pci/samsung,exynos-pcie.yaml     | 106 ++++++++++++++++++
>  1 file changed, 106 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
> new file mode 100644
> index 000000000000..48fb569c238c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
> @@ -0,0 +1,104 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung SoC series PCIe Host Controller Device Tree Bindings
> +
> +maintainers:
> +  - Jaehoon Chung <[e-mail]>
> +
> +description: |+
> +  Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
> +  PCIe IP and thus inherits all the common properties defined in
> +  designware-pcie.txt.
> +
> +allOf:
> +  - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> +  compatible:
> +    enum:
> +      - samsung,exynos5433-pcie

const, not enum

> +
> +  reg:
> +    items:
> +      - description: External Local Bus interface (ELBI) registers.
> +      - description: Data Bus Interface (DBI) registers.
> +      - description: PCIe configuration space region.
> +
> +  reg-names:
> +    items:
> +      - const: elbi
> +      - const: bdi
> +      - const: config
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: PCIe bridge clock
> +      - description: PCIe bus clock
> +
> +  clock-names:
> +    items:
> +      - const: pcie
> +      - const: pcie_bus
> +
> +  phys:
> +    maxItems: 1
> +
> +  phy-names:
> +    const: pcie-phy
> +
> +  vdd10-supply:
> +    description:
> +      Phandle to a regulator that provides 1.0V power to the PCIe block.
> +
> +  vdd18-supply:
> +    description:
> +      Phandle to a regulator that provides 1.8V power to the PCIe block.
> +
> +required:
> +  - reg
> +  - reg-names
> +  - interrupts
> +  - interrupt-names
> +  - clocks
> +  - clock-names
> +  - phys
> +  - phy-names
> +  - vdd10-supply

additionalProperties: false

Best regards,
Krzysztof

Krzysztof Kozlowski Oct. 19, 2020, 10:18 a.m. UTC | #2

On Mon, 19 Oct 2020 at 12:12, Krzysztof Kozlowski <[e-mail]> wrote:
>
> On Mon, Oct 19, 2020 at 11:47:11AM +0200, Marek Szyprowski wrote:
> > From: Jaehoon Chung <[e-mail]>
> >
> > Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433
> > variant).
>
> The title has typo and actually entire "Doc" should be dropped. Just
> "dt-bindings: pci:".  This applies to all DT patches.
>
> >
> > Signed-off-by: Jaehoon Chung <[e-mail]>
> > [mszyprow: updated the binding to latest driver changes, rewrote it in yaml,
> >          rewrote commit message]
>
> If you wrote them in YAML it should be a new patch of yours. It is the
> same then as converting TXT to YAML.
>
> > Signed-off-by: Marek Szyprowski <[e-mail]>
> > ---
> >  .../bindings/pci/samsung,exynos-pcie.yaml     | 106 ++++++++++++++++++
> >  1 file changed, 106 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
> > new file mode 100644
> > index 000000000000..48fb569c238c
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
> > @@ -0,0 +1,104 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Samsung SoC series PCIe Host Controller Device Tree Bindings
> > +
> > +maintainers:
> > +  - Jaehoon Chung <[e-mail]>
> > +
> > +description: |+
> > +  Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
> > +  PCIe IP and thus inherits all the common properties defined in
> > +  designware-pcie.txt.
> > +
> > +allOf:
> > +  - $ref: /schemas/pci/pci-bus.yaml#
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - samsung,exynos5433-pcie
>
> const, not enum
>
> > +
> > +  reg:
> > +    items:
> > +      - description: External Local Bus interface (ELBI) registers.
> > +      - description: Data Bus Interface (DBI) registers.
> > +      - description: PCIe configuration space region.
> > +
> > +  reg-names:
> > +    items:
> > +      - const: elbi
> > +      - const: bdi
> > +      - const: config
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: PCIe bridge clock
> > +      - description: PCIe bus clock
> > +
> > +  clock-names:
> > +    items:
> > +      - const: pcie
> > +      - const: pcie_bus
> > +
> > +  phys:
> > +    maxItems: 1
> > +
> > +  phy-names:
> > +    const: pcie-phy
> > +
> > +  vdd10-supply:
> > +    description:
> > +      Phandle to a regulator that provides 1.0V power to the PCIe block.
> > +
> > +  vdd18-supply:
> > +    description:
> > +      Phandle to a regulator that provides 1.8V power to the PCIe block.
> > +
> > +required:
> > +  - reg
> > +  - reg-names
> > +  - interrupts
> > +  - interrupt-names
> > +  - clocks
> > +  - clock-names
> > +  - phys
> > +  - phy-names
> > +  - vdd10-supply
>
> additionalProperties: false

This can be unevaluatedProperties, since you include pci-bus schema.
However still you should either include designware schema or include
it's properties here.

Best regards,
Krzysztof

Krzysztof Kozlowski Oct. 19, 2020, 10:28 a.m. UTC | #3

On Mon, Oct 19, 2020 at 11:47:11AM +0200, Marek Szyprowski wrote:
> From: Jaehoon Chung <[e-mail]>
> 
> Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433
> variant).
> 
> Signed-off-by: Jaehoon Chung <[e-mail]>
> [mszyprow: updated the binding to latest driver changes, rewrote it in yaml,
> 	   rewrote commit message]
> Signed-off-by: Marek Szyprowski <[e-mail]>
> ---
>  .../bindings/pci/samsung,exynos-pcie.yaml     | 106 ++++++++++++++++++
>  1 file changed, 106 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
> new file mode 100644
> index 000000000000..48fb569c238c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
> @@ -0,0 +1,104 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung SoC series PCIe Host Controller Device Tree Bindings
> +
> +maintainers:
> +  - Jaehoon Chung <[e-mail]>
> +
> +description: |+
> +  Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
> +  PCIe IP and thus inherits all the common properties defined in
> +  designware-pcie.txt.
> +
> +allOf:
> +  - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> +  compatible:
> +    enum:
> +      - samsung,exynos5433-pcie
> +
> +  reg:
> +    items:
> +      - description: External Local Bus interface (ELBI) registers.
> +      - description: Data Bus Interface (DBI) registers.
> +      - description: PCIe configuration space region.
> +
> +  reg-names:
> +    items:
> +      - const: elbi
> +      - const: bdi
> +      - const: config
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: PCIe bridge clock
> +      - description: PCIe bus clock
> +
> +  clock-names:
> +    items:
> +      - const: pcie
> +      - const: pcie_bus
> +
> +  phys:
> +    maxItems: 1
> +
> +  phy-names:
> +    const: pcie-phy
> +
> +  vdd10-supply:
> +    description:
> +      Phandle to a regulator that provides 1.0V power to the PCIe block.
> +
> +  vdd18-supply:
> +    description:
> +      Phandle to a regulator that provides 1.8V power to the PCIe block.
> +
> +required:
> +  - reg
> +  - reg-names
> +  - interrupts
> +  - interrupt-names
> +  - clocks
> +  - clock-names
> +  - phys
> +  - phy-names
> +  - vdd10-supply
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/exynos5433.h>
> +
> +    pcie: pcie@15700000 {
> +        compatible = "samsung,exynos5433-pcie";
> +        reg = <0x156b0000 0x1000>, <0x15700000 0x1000>, <0x0c000000 0x1000>;
> +        reg-names = "elbi", "dbi", "config";

You have a typo here. This does not pass dt_binbind_check.

> +        #address-cells = <3>;
> +        #size-cells = <2>;
> +        #interrupt-cells = <1>;
> +        device_type = "pci";
> +        interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
> +        clock-names = "pcie", "pcie_bus";
> +        phys = <&pcie_phy>;
> +        phy-names = "pcie-phy";
> +        pinctrl-names = "default";
> +        pinctrl-0 = <&pcie_bus &pcie_wlanen>;
> +        num-lanes = <1>;
> +        bus-range = <0x00 0xff>;
> +        ranges = <0x81000000 0 0	  0x0c001000 0 0x00010000>,
> +                 <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
> +        vdd10-supply = <&ldo6_reg>;
> +        vdd18-supply = <&ldo7_reg>;
> +        iterrupt-map-mask = <0 0 0 0>;
> +        interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;

This does not pass dt_binbind_check - your own bindings. You require
interrupt-names.

Best regards,
Krzysztof

Rob Herring Oct. 19, 2020, 1:38 p.m. UTC | #4

On Mon, Oct 19, 2020 at 4:47 AM Marek Szyprowski
<[e-mail]> wrote:
>
> From: Jaehoon Chung <[e-mail]>
>
> Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433
> variant).
>
> Signed-off-by: Jaehoon Chung <[e-mail]>
> [mszyprow: updated the binding to latest driver changes, rewrote it in yaml,
>            rewrote commit message]
> Signed-off-by: Marek Szyprowski <[e-mail]>
> ---
>  .../bindings/pci/samsung,exynos-pcie.yaml     | 106 ++++++++++++++++++
>  1 file changed, 106 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
> new file mode 100644
> index 000000000000..48fb569c238c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
> @@ -0,0 +1,104 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung SoC series PCIe Host Controller Device Tree Bindings
> +
> +maintainers:
> +  - Jaehoon Chung <[e-mail]>
> +
> +description: |+
> +  Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
> +  PCIe IP and thus inherits all the common properties defined in
> +  designware-pcie.txt.
> +
> +allOf:
> +  - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> +  compatible:
> +    enum:
> +      - samsung,exynos5433-pcie
> +
> +  reg:
> +    items:
> +      - description: External Local Bus interface (ELBI) registers.
> +      - description: Data Bus Interface (DBI) registers.
> +      - description: PCIe configuration space region.
> +
> +  reg-names:
> +    items:
> +      - const: elbi
> +      - const: bdi

dbi

> +      - const: config
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: PCIe bridge clock
> +      - description: PCIe bus clock
> +
> +  clock-names:
> +    items:
> +      - const: pcie
> +      - const: pcie_bus
> +
> +  phys:
> +    maxItems: 1
> +
> +  phy-names:
> +    const: pcie-phy

Kind of a pointless name.

> +
> +  vdd10-supply:
> +    description:
> +      Phandle to a regulator that provides 1.0V power to the PCIe block.
> +
> +  vdd18-supply:
> +    description:
> +      Phandle to a regulator that provides 1.8V power to the PCIe block.
> +
> +required:
> +  - reg
> +  - reg-names
> +  - interrupts
> +  - interrupt-names
> +  - clocks
> +  - clock-names
> +  - phys
> +  - phy-names
> +  - vdd10-supply
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/exynos5433.h>
> +
> +    pcie: pcie@15700000 {
> +        compatible = "samsung,exynos5433-pcie";
> +        reg = <0x156b0000 0x1000>, <0x15700000 0x1000>, <0x0c000000 0x1000>;
> +        reg-names = "elbi", "dbi", "config";
> +        #address-cells = <3>;
> +        #size-cells = <2>;
> +        #interrupt-cells = <1>;
> +        device_type = "pci";
> +        interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
> +        clock-names = "pcie", "pcie_bus";
> +        phys = <&pcie_phy>;
> +        phy-names = "pcie-phy";
> +        pinctrl-names = "default";
> +        pinctrl-0 = <&pcie_bus &pcie_wlanen>;
> +        num-lanes = <1>;
> +        bus-range = <0x00 0xff>;
> +        ranges = <0x81000000 0 0         0x0c001000 0 0x00010000>,
> +                 <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
> +        vdd10-supply = <&ldo6_reg>;
> +        vdd18-supply = <&ldo7_reg>;
> +        iterrupt-map-mask = <0 0 0 0>;

typo

> +        interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
> +    };
> --
> 2.17.1
>

Marek Szyprowski Oct. 21, 2020, 11:59 a.m. UTC | #5

Hi Krzysztof,

On 19.10.2020 12:18, Krzysztof Kozlowski wrote:
> On Mon, 19 Oct 2020 at 12:12, Krzysztof Kozlowski <[e-mail]> wrote:
>> On Mon, Oct 19, 2020 at 11:47:11AM +0200, Marek Szyprowski wrote:
>>> From: Jaehoon Chung <[e-mail]>
>>>
>>> Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433
>>> variant).
>> The title has typo and actually entire "Doc" should be dropped. Just
>> "dt-bindings: pci:".  This applies to all DT patches.
>>
>>> Signed-off-by: Jaehoon Chung <[e-mail]>
>>> [mszyprow: updated the binding to latest driver changes, rewrote it in yaml,
>>>           rewrote commit message]
>> If you wrote them in YAML it should be a new patch of yours. It is the
>> same then as converting TXT to YAML.
>>
>>> Signed-off-by: Marek Szyprowski <[e-mail]>
>>> ---
>>>   .../bindings/pci/samsung,exynos-pcie.yaml     | 106 ++++++++++++++++++
>>>   1 file changed, 106 insertions(+)
>>>   create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
>>> new file mode 100644
>>> index 000000000000..48fb569c238c
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
>>> @@ -0,0 +1,104 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: https://protect2.fireeye.com/v1/url?k=a6caf3f8-fb18e55d-a6cb78b7-0cc47a31bee8-bb3776dee0a03bbb&q=1&e=5f1b0c1e-e4d1-4ae2-b527-8cd5ec52695f&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fpci%2Fsamsung%2Cexynos-pcie.yaml%23
>>> +$schema: https://protect2.fireeye.com/v1/url?k=591573a2-04c76507-5914f8ed-0cc47a31bee8-bd08b2eac7a5040d&q=1&e=5f1b0c1e-e4d1-4ae2-b527-8cd5ec52695f&u=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23
>>> +
>>> +title: Samsung SoC series PCIe Host Controller Device Tree Bindings
>>> +
>>> +maintainers:
>>> +  - Jaehoon Chung <[e-mail]>
>>> +
>>> +description: |+
>>> +  Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
>>> +  PCIe IP and thus inherits all the common properties defined in
>>> +  designware-pcie.txt.
>>> +
>>> +allOf:
>>> +  - $ref: /schemas/pci/pci-bus.yaml#
>>> +
>>> +properties:
>>> +  compatible:
>>> +    enum:
>>> +      - samsung,exynos5433-pcie
>> const, not enum
>>
>>> +
>>> +  reg:
>>> +    items:
>>> +      - description: External Local Bus interface (ELBI) registers.
>>> +      - description: Data Bus Interface (DBI) registers.
>>> +      - description: PCIe configuration space region.
>>> +
>>> +  reg-names:
>>> +    items:
>>> +      - const: elbi
>>> +      - const: bdi
>>> +      - const: config
>>> +
>>> +  interrupts:
>>> +    maxItems: 1
>>> +
>>> +  clocks:
>>> +    items:
>>> +      - description: PCIe bridge clock
>>> +      - description: PCIe bus clock
>>> +
>>> +  clock-names:
>>> +    items:
>>> +      - const: pcie
>>> +      - const: pcie_bus
>>> +
>>> +  phys:
>>> +    maxItems: 1
>>> +
>>> +  phy-names:
>>> +    const: pcie-phy
>>> +
>>> +  vdd10-supply:
>>> +    description:
>>> +      Phandle to a regulator that provides 1.0V power to the PCIe block.
>>> +
>>> +  vdd18-supply:
>>> +    description:
>>> +      Phandle to a regulator that provides 1.8V power to the PCIe block.
>>> +
>>> +required:
>>> +  - reg
>>> +  - reg-names
>>> +  - interrupts
>>> +  - interrupt-names
>>> +  - clocks
>>> +  - clock-names
>>> +  - phys
>>> +  - phy-names
>>> +  - vdd10-supply
>> additionalProperties: false
> This can be unevaluatedProperties, since you include pci-bus schema.
> However still you should either include designware schema or include
> it's properties here.

Frankly, I would like to include designware-pci bindling/schema, but it 
has not been converted to yaml yet. I don't feel that I know PCI enough 
to do that conversion...

Best regards

Marek Szyprowski Oct. 21, 2020, 12:05 p.m. UTC | #6

Hi Rob,

On 19.10.2020 15:38, Rob Herring wrote:
> On Mon, Oct 19, 2020 at 4:47 AM Marek Szyprowski
> <[e-mail]> wrote:
>> From: Jaehoon Chung <[e-mail]>
>>
>> Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433
>> variant).
>>
>> Signed-off-by: Jaehoon Chung <[e-mail]>
>> [mszyprow: updated the binding to latest driver changes, rewrote it in yaml,
>>             rewrote commit message]
>> Signed-off-by: Marek Szyprowski <[e-mail]>
>> ---
>>   .../bindings/pci/samsung,exynos-pcie.yaml     | 106 ++++++++++++++++++
>>   1 file changed, 106 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
>> new file mode 100644
>> index 000000000000..48fb569c238c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
>> @@ -0,0 +1,104 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: https://protect2.fireeye.com/v1/url?k=3dfd0348-6067aaeb-3dfc8807-002590f5b904-a68fd848316a7cc4&q=1&e=261ae2d1-4457-43b7-8727-35f3cfbc45c0&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fpci%2Fsamsung%2Cexynos-pcie.yaml%23
>> +$schema: https://protect2.fireeye.com/v1/url?k=ab825ba1-f618f202-ab83d0ee-002590f5b904-4aba44c12cb70753&q=1&e=261ae2d1-4457-43b7-8727-35f3cfbc45c0&u=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23
>> +
>> +title: Samsung SoC series PCIe Host Controller Device Tree Bindings
>> +
>> +maintainers:
>> +  - Jaehoon Chung <[e-mail]>
>> +
>> +description: |+
>> +  Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
>> +  PCIe IP and thus inherits all the common properties defined in
>> +  designware-pcie.txt.
>> +
>> +allOf:
>> +  - $ref: /schemas/pci/pci-bus.yaml#
>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - samsung,exynos5433-pcie
>> +
>> +  reg:
>> +    items:
>> +      - description: External Local Bus interface (ELBI) registers.
>> +      - description: Data Bus Interface (DBI) registers.
>> +      - description: PCIe configuration space region.
>> +
>> +  reg-names:
>> +    items:
>> +      - const: elbi
>> +      - const: bdi
> dbi
>
>> +      - const: config
>> +
>> +  interrupts:
>> +    maxItems: 1
>> +
>> +  clocks:
>> +    items:
>> +      - description: PCIe bridge clock
>> +      - description: PCIe bus clock
>> +
>> +  clock-names:
>> +    items:
>> +      - const: pcie
>> +      - const: pcie_bus
>> +
>> +  phys:
>> +    maxItems: 1
>> +
>> +  phy-names:
>> +    const: pcie-phy
> Kind of a pointless name.

Most of the other PCI(e) drivers uses such:

# git grep "phy-names =" Documentation/devicetree/bindings/pci/

Do you want me to change it to simple "pcie"?

>> +
>> +  vdd10-supply:
>> +    description:
>> +      Phandle to a regulator that provides 1.0V power to the PCIe block.
>> +
>> +  vdd18-supply:
>> +    description:
>> +      Phandle to a regulator that provides 1.8V power to the PCIe block.
>> +
>> +required:
>> +  - reg
>> +  - reg-names
>> +  - interrupts
>> +  - interrupt-names
>> +  - clocks
>> +  - clock-names
>> +  - phys
>> +  - phy-names
>> +  - vdd10-supply
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/irq.h>
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/clock/exynos5433.h>
>> +
>> +    pcie: pcie@15700000 {
>> +        compatible = "samsung,exynos5433-pcie";
>> +        reg = <0x156b0000 0x1000>, <0x15700000 0x1000>, <0x0c000000 0x1000>;
>> +        reg-names = "elbi", "dbi", "config";
>> +        #address-cells = <3>;
>> +        #size-cells = <2>;
>> +        #interrupt-cells = <1>;
>> +        device_type = "pci";
>> +        interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
>> +        clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
>> +        clock-names = "pcie", "pcie_bus";
>> +        phys = <&pcie_phy>;
>> +        phy-names = "pcie-phy";
>> +        pinctrl-names = "default";
>> +        pinctrl-0 = <&pcie_bus &pcie_wlanen>;
>> +        num-lanes = <1>;
>> +        bus-range = <0x00 0xff>;
>> +        ranges = <0x81000000 0 0         0x0c001000 0 0x00010000>,
>> +                 <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
>> +        vdd10-supply = <&ldo6_reg>;
>> +        vdd18-supply = <&ldo7_reg>;
>> +        iterrupt-map-mask = <0 0 0 0>;
> typo
>
>> +        interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
>> +    };
>> --
>> 2.17.1
>>
Best regards

Krzysztof Kozlowski Oct. 21, 2020, 12:12 p.m. UTC | #7

On Wed, Oct 21, 2020 at 01:59:25PM +0200, Marek Szyprowski wrote:
 >>> +required:
> >>> +  - reg
> >>> +  - reg-names
> >>> +  - interrupts
> >>> +  - interrupt-names
> >>> +  - clocks
> >>> +  - clock-names
> >>> +  - phys
> >>> +  - phy-names
> >>> +  - vdd10-supply
> >> additionalProperties: false
> > This can be unevaluatedProperties, since you include pci-bus schema.
> > However still you should either include designware schema or include
> > it's properties here.
> 
> Frankly, I would like to include designware-pci bindling/schema, but it 
> has not been converted to yaml yet. I don't feel that I know PCI enough 
> to do that conversion...

I think you need then include all properties in your dtschema. Otherwise
DTS will not pass (neither the example here) the checks.

Best regards,
Krzysztof

Patch

diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
new file mode 100644
index 000000000000..48fb569c238c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
@@ -0,0 +1,104 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series PCIe Host Controller Device Tree Bindings
+
+maintainers:
+  - Jaehoon Chung <[e-mail]>
+
+description: |+
+  Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
+  PCIe IP and thus inherits all the common properties defined in
+  designware-pcie.txt.
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    enum:
+      - samsung,exynos5433-pcie
+
+  reg:
+    items:
+      - description: External Local Bus interface (ELBI) registers.
+      - description: Data Bus Interface (DBI) registers.
+      - description: PCIe configuration space region.
+
+  reg-names:
+    items:
+      - const: elbi
+      - const: bdi
+      - const: config
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: PCIe bridge clock
+      - description: PCIe bus clock
+
+  clock-names:
+    items:
+      - const: pcie
+      - const: pcie_bus
+
+  phys:
+    maxItems: 1
+
+  phy-names:
+    const: pcie-phy
+
+  vdd10-supply:
+    description:
+      Phandle to a regulator that provides 1.0V power to the PCIe block.
+
+  vdd18-supply:
+    description:
+      Phandle to a regulator that provides 1.8V power to the PCIe block.
+
+required:
+  - reg
+  - reg-names
+  - interrupts
+  - interrupt-names
+  - clocks
+  - clock-names
+  - phys
+  - phy-names
+  - vdd10-supply
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/exynos5433.h>
+
+    pcie: pcie@15700000 {
+        compatible = "samsung,exynos5433-pcie";
+        reg = <0x156b0000 0x1000>, <0x15700000 0x1000>, <0x0c000000 0x1000>;
+        reg-names = "elbi", "dbi", "config";
+        #address-cells = <3>;
+        #size-cells = <2>;
+        #interrupt-cells = <1>;
+        device_type = "pci";
+        interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
+        clock-names = "pcie", "pcie_bus";
+        phys = <&pcie_phy>;
+        phy-names = "pcie-phy";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pcie_bus &pcie_wlanen>;
+        num-lanes = <1>;
+        bus-range = <0x00 0xff>;
+        ranges = <0x81000000 0 0	  0x0c001000 0 0x00010000>,
+                 <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
+        vdd10-supply = <&ldo6_reg>;
+        vdd18-supply = <&ldo7_reg>;
+        iterrupt-map-mask = <0 0 0 0>;
+        interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+    };