| Message ID | 20201019094715.15343-4-m.szyprowski@samsung.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Add DW PCIe support for Exynos5433 SoCs | expand |
On Mon, Oct 19, 2020 at 11:47:12AM +0200, Marek Szyprowski wrote: > From: Jaehoon Chung <jh80.chung@samsung.com> > > Add dt-bindings for the Samsung Exynos PCIe PHY controller (Exynos5433 > variant). > > Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> > [mszyprow: updated the binding to latest driver changes, rewrote it in yaml, > rewrote commit message] The same as for 2/6 - conversion of TXT to YAML is like a new patch. It is quite significant work. > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> > --- > .../bindings/phy/samsung,exynos-pcie-phy.yaml | 51 +++++++++++++++++++ > 1 file changed, 51 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml > new file mode 100644 > index 000000000000..ce92d1e687e7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml > @@ -0,0 +1,51 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Samsung SoC series PCIe PHY Device Tree Bindings > + > +maintainers: > + - Jaehoon Chung <jh80.chung@samsung.com> > + > +properties: > + "#phy-cells": > + const: 0 > + > + compatible: > + enum: > + - samsung,exynos5433-pcie-phy enum->const Best regards, Krzysztof
On Mon, 19 Oct 2020 11:47:12 +0200, Marek Szyprowski wrote: > From: Jaehoon Chung <jh80.chung@samsung.com> > > Add dt-bindings for the Samsung Exynos PCIe PHY controller (Exynos5433 > variant). > > Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> > [mszyprow: updated the binding to latest driver changes, rewrote it in yaml, > rewrote commit message] > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> > --- > .../bindings/phy/samsung,exynos-pcie-phy.yaml | 51 +++++++++++++++++++ > 1 file changed, 51 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml > My bot found errors running 'make dt_binding_check' on your patch: ./Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml:51:4: [error] no new line character at the end of file (new-line-at-end-of-file) make[1]: *** [Documentation/devicetree/bindings/Makefile:59: Documentation/devicetree/bindings/processed-schema-examples.json] Error 123 make: *** [Makefile:1366: dt_binding_check] Error 2 See https://patchwork.ozlabs.org/patch/1384137 If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure dt-schema is up to date: pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade Please check and re-submit.
diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml new file mode 100644 index 000000000000..ce92d1e687e7 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC series PCIe PHY Device Tree Bindings + +maintainers: + - Jaehoon Chung <jh80.chung@samsung.com> + +properties: + "#phy-cells": + const: 0 + + compatible: + enum: + - samsung,exynos5433-pcie-phy + + reg: + maxItems: 1 + + samsung,pmu-syscon: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for PMU system controller interface, used to + control PMU registers bits for PCIe PHY + + samsung,fsys-sysreg: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: phandle for FSYS sysreg interface, used to control + sysreg registers bits for PCIe PHY + +required: + - "#phy-cells" + - compatible + - reg + - samsung,pmu-syscon + - samsung,fsys-sysreg + +additionalProperties: false + +examples: + - | + pcie_phy: pcie-phy@15680000 { + compatible = "samsung,exynos5433-pcie-phy"; + reg = <0x15680000 0x1000>; + samsung,pmu-syscon = <&pmu_system_controller>; + samsung,fsys-sysreg = <&syscon_fsys>; + #phy-cells = <0>; + }; +... \ No newline at end of file