| Message ID | 20201022171639.773702-1-aford173@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: imx8mm: Add GPU node | expand |
On 10/22/20 7:16 PM, Adam Ford wrote: > According to the documentation from NXP, the i.MX8M Nano has a > Vivante GC7000 Ultra Lite as its GPU core. > > With this patch, the Etnaviv driver presents the GPU as: > etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203 > > It uses the GPCV2 controller to enable the power domain for the GPU. Subject should say 8mn , not 8mm . Are the assigned-clock-rates correct ?
On Thu, Oct 22, 2020 at 1:17 PM Marek Vasut <marex@denx.de> wrote: > > On 10/22/20 7:16 PM, Adam Ford wrote: > > According to the documentation from NXP, the i.MX8M Nano has a > > Vivante GC7000 Ultra Lite as its GPU core. > > > > With this patch, the Etnaviv driver presents the GPU as: > > etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203 > > > > It uses the GPCV2 controller to enable the power domain for the GPU. > > Subject should say 8mn , not 8mm . ugh.. My mistake. I'll submit a V2 once other have had a chance to give some feedback. Maybe NXP can comment on the dialog below. > > Are the assigned-clock-rates correct ? I used the assigned clock rates from the vendor kernel, with the exception of running at 400MHz instead of 600MHz. According to the datasheet, the GPU clock needs to be 400MHZ to run at 0.85V. The 600MHz operating point for the GPU requires a 0.95V operating point. Since the default operating point for the Nano shows 0.85V, I left the GPU clock lower to match the normal operating speed. This varies a bit from the vendor kernel, but their kernel is also showing a 0.95V operating point, so I think that's why they are specifying a 600MHz operating point. On the Beacon embedded board, we're driving the LPDDR to 800MHz which requires the ARM to run at .95V. I was able to override the assigned-clock rates for my board to run at 600MHz, and change the ARM operating point to .95V to meet the spec. My intent was to use the defaults and let the board files override them. If you want, I can try to look through the board files to see what operating point their using and propose updates to those respective device trees to address the clocks on those boards. adam
On Do, 2020-10-22 at 13:31 -0500, Adam Ford wrote: > On Thu, Oct 22, 2020 at 1:17 PM Marek Vasut <marex@denx.de> wrote: > > On 10/22/20 7:16 PM, Adam Ford wrote: > > > According to the documentation from NXP, the i.MX8M Nano has a > > > Vivante GC7000 Ultra Lite as its GPU core. > > > > > > With this patch, the Etnaviv driver presents the GPU as: > > > etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203 > > > > > > It uses the GPCV2 controller to enable the power domain for the > > > GPU. > > > > Subject should say 8mn , not 8mm . > > ugh.. My mistake. I'll submit a V2 once other have had a chance to > give some feedback. > > Maybe NXP can comment on the dialog below. > > > Are the assigned-clock-rates correct ? > > I used the assigned clock rates from the vendor kernel, with the > exception of running at 400MHz instead of 600MHz. According to the > datasheet, the GPU clock needs to be 400MHZ to run at 0.85V. The > 600MHz operating point for the GPU requires a 0.95V operating point. > Since the default operating point for the Nano shows 0.85V, I left > the > GPU clock lower to match the normal operating speed. This varies a > bit from the vendor kernel, but their kernel is also showing a 0.95V > operating point, so I think that's why they are specifying a 600MHz > operating point. > > On the Beacon embedded board, we're driving the LPDDR to 800MHz which > requires the ARM to run at .95V. I was able to override the > assigned-clock rates for my board to run at 600MHz, and change the > ARM > operating point to .95V to meet the spec. > > My intent was to use the defaults and let the board files override > them. If you want, I can try to look through the board files to see > what operating point their using and propose updates to those > respective device trees to address the clocks on those boards. I think this is fine as-is with this explanation. At least we have a precedent in the i.MX8MQ DT where the assigned clocks are for the base (non overdrive) operating point and boards can choose to override it if they want to use the overdrive OPP. At least until we add proper frequency scaling in etnaviv, which should obsolete those fixed clock rates. Regards, Lucas
On Thu, Oct 22, 2020 at 12:16:39PM -0500, Adam Ford wrote: > According to the documentation from NXP, the i.MX8M Nano has a > Vivante GC7000 Ultra Lite as its GPU core. > > With this patch, the Etnaviv driver presents the GPU as: > etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203 > > It uses the GPCV2 controller to enable the power domain for the GPU. > > Signed-off-by: Adam Ford <aford173@gmail.com> > --- > This patch depends on a series located: > https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=368903 > and > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > index 605e6dbd2c6f..62c8cd3dea7c 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -4,6 +4,8 @@ > */ > > #include <dt-bindings/clock/imx8mn-clock.h> > +#include <dt-bindings/power/imx8mn-power.h> > +#include <dt-bindings/reset/imx8mq-reset.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/input/input.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > @@ -1019,6 +1021,31 @@ gpmi: nand-controller@33002000 { > status = "disabled"; > }; > > + gpu: gpu@38000000 { > + compatible = "vivante,gc"; > + reg = <0x38000000 0x8000>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MN_CLK_GPU_AHB>, > + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MN_CLK_GPU_CORE_ROOT>, > + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; > + clock-names = "reg", "bus", "core", "shader"; > + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, > + <&clk IMX8MN_CLK_GPU_SHADER_SRC>, > + <&clk IMX8MN_CLK_GPU_AXI>, > + <&clk IMX8MN_CLK_GPU_AHB>, > + <&clk IMX8MN_GPU_PLL>, > + <&clk IMX8MN_CLK_GPU_CORE_DIV>, > + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; > + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, > + <&clk IMX8MN_GPU_PLL_OUT>, > + <&clk IMX8MN_SYS_PLL1_800M>, > + <&clk IMX8MN_SYS_PLL1_800M>; > + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, > + <400000000>, <400000000>; Plaese indent it till '=' and put each entry in new line. This will match other 'assigned-clock' properties. Best regards, Krzysztof
On Fri, Oct 23, 2020 at 3:25 AM Lucas Stach <l.stach@pengutronix.de> wrote: > > On Do, 2020-10-22 at 13:31 -0500, Adam Ford wrote: > > On Thu, Oct 22, 2020 at 1:17 PM Marek Vasut <marex@denx.de> wrote: > > > On 10/22/20 7:16 PM, Adam Ford wrote: > > > > According to the documentation from NXP, the i.MX8M Nano has a > > > > Vivante GC7000 Ultra Lite as its GPU core. > > > > > > > > With this patch, the Etnaviv driver presents the GPU as: > > > > etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203 > > > > > > > > It uses the GPCV2 controller to enable the power domain for the > > > > GPU. > > > > > > Subject should say 8mn , not 8mm . > > > > ugh.. My mistake. I'll submit a V2 once other have had a chance to > > give some feedback. > > > > Maybe NXP can comment on the dialog below. > > > > > Are the assigned-clock-rates correct ? > > > > I used the assigned clock rates from the vendor kernel, with the > > exception of running at 400MHz instead of 600MHz. According to the > > datasheet, the GPU clock needs to be 400MHZ to run at 0.85V. The > > 600MHz operating point for the GPU requires a 0.95V operating point. > > Since the default operating point for the Nano shows 0.85V, I left > > the > > GPU clock lower to match the normal operating speed. This varies a > > bit from the vendor kernel, but their kernel is also showing a 0.95V > > operating point, so I think that's why they are specifying a 600MHz > > operating point. > > > > On the Beacon embedded board, we're driving the LPDDR to 800MHz which > > requires the ARM to run at .95V. I was able to override the > > assigned-clock rates for my board to run at 600MHz, and change the > > ARM > > operating point to .95V to meet the spec. > > > > My intent was to use the defaults and let the board files override > > them. If you want, I can try to look through the board files to see > > what operating point their using and propose updates to those > > respective device trees to address the clocks on those boards. > > I think this is fine as-is with this explanation. At least we have a > precedent in the i.MX8MQ DT where the assigned clocks are for the base > (non overdrive) operating point and boards can choose to override it if > they want to use the overdrive OPP. At least until we add proper > frequency scaling in etnaviv, which should obsolete those fixed clock > rates. I have to do a V2 from the feedback of Krzysztof. I will expand the commit message to include the description of the 400MHz vs 600MHz clocking and the need for adjusting the operating points. adam > > Regards, > Lucas >
Hi Adam,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on shawnguo/for-next rockchip/for-next soc/for-next keystone/next arm64/for-next/core arm/for-next kvmarm/next v5.9 next-20201023]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Adam-Ford/arm64-dts-imx8mm-Add-GPU-node/20201023-011724
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r032-20201022 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 147b9497e79a98a8614b2b5eb4ba653b44f6b6f0)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/0day-ci/linux/commit/ab5285961d9a4c236f47b1c2ad3e25e0aee987be
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Adam-Ford/arm64-dts-imx8mm-Add-GPU-node/20201023-011724
git checkout ab5285961d9a4c236f47b1c2ad3e25e0aee987be
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from arch/arm64/boot/dts/freescale/imx8mn-evk.dts:8:
>> arch/arm64/boot/dts/freescale/imx8mn.dtsi:7:10: fatal error: 'dt-bindings/power/imx8mn-power.h' file not found
#include <dt-bindings/power/imx8mn-power.h>
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1 error generated.
vim +7 arch/arm64/boot/dts/freescale/imx8mn.dtsi
> 7 #include <dt-bindings/power/imx8mn-power.h>
8 #include <dt-bindings/reset/imx8mq-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
13
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 605e6dbd2c6f..62c8cd3dea7c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -4,6 +4,8 @@ */ #include <dt-bindings/clock/imx8mn-clock.h> +#include <dt-bindings/power/imx8mn-power.h> +#include <dt-bindings/reset/imx8mq-reset.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -1019,6 +1021,31 @@ gpmi: nand-controller@33002000 { status = "disabled"; }; + gpu: gpu@38000000 { + compatible = "vivante,gc"; + reg = <0x38000000 0x8000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; + clock-names = "reg", "bus", "core", "shader"; + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, + <&clk IMX8MN_CLK_GPU_SHADER_SRC>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>, + <&clk IMX8MN_CLK_GPU_CORE_DIV>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, + <400000000>, <400000000>; + power-domains = <&pgc_gpumix>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>,
According to the documentation from NXP, the i.MX8M Nano has a Vivante GC7000 Ultra Lite as its GPU core. With this patch, the Etnaviv driver presents the GPU as: etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203 It uses the GPCV2 controller to enable the power domain for the GPU. Signed-off-by: Adam Ford <aford173@gmail.com> --- This patch depends on a series located: https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=368903 and