| Message ID | 20201022165751.771695-1-aford173@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: imx: Add Beacon i.MX8M Nano development kit | expand |
Hi Adam,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on shawnguo/for-next]
[also build test ERROR on soc/for-next next-20201022]
[cannot apply to robh/for-next rockchip/for-next keystone/next arm64/for-next/core clk/clk-next arm/for-next xlnx/master kvmarm/next v5.9]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Adam-Ford/arm64-dts-imx-Add-Beacon-i-MX8M-Nano-development-kit/20201023-005857
base: https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/ec137628378cd7a0840b591f3893dd5fa3370f00
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Adam-Ford/arm64-dts-imx-Add-Beacon-i-MX8M-Nano-development-kit/20201023-005857
git checkout ec137628378cd7a0840b591f3893dd5fa3370f00
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi:155.1-7 Label or path easrc not found
>> Error: arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi:160.1-6 Label or path sai3 not found
FATAL ERROR: Syntax error parsing input tree
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
On Thu, Oct 22, 2020 at 11:57:50AM -0500, Adam Ford wrote: > Beacon Embeddedworks is launching a development kit based on the > i.MX8M Nano SoC. The kit consists of a System on Module (SOM) > + baseboard. The SOM has the SoC, eMMC, and Ethernet. The baseboard > has an wm8962 audio CODEC, and a single USB OTG. > > Signed-off-by: Adam Ford <aford173@gmail.com> > --- > Based on top of previous series found: > https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=366931 > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index c7890b622587..ab47b3b1de75 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi > new file mode 100644 > index 000000000000..898715aa79b5 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi > @@ -0,0 +1,313 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright 2020 Compass Electronics Group, LLC > + */ > + > +/ { > + leds { > + compatible = "gpio-leds"; > + > + led0 { led-0 > + label = "gen_led0"; > + gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; > + default-state = "off"; > + }; > + > + led1 { > + label = "gen_led1"; > + gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; > + default-state = "off"; > + }; > + > + led2 { > + label = "gen_led2"; > + gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; > + default-state = "off"; > + }; > + > + led3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_led3>; > + label = "heartbeat"; > + gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "heartbeat"; > + }; > + }; > + > + reg_audio: regulator-audio { > + compatible = "regulator-fixed"; > + regulator-name = "3v3_aud"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + reg_usdhc2_vmmc: regulator-usdhc2 { > + compatible = "regulator-fixed"; > + regulator-name = "VSD_3V3"; lowercase name please to match everything else. > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + reg_usb_otg_vbus: regulator-usb { > + compatible = "regulator-fixed"; > + pinctrl-0 = <&pinctrl_reg_usb_otg>; pinctrl-names... and test whether it really works after this change. Without it the pinctrl was probably not applied. > + regulator-name = "usb_otg_vbus"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + sound { > + compatible = "fsl,imx-audio-wm8962"; > + model = "wm8962-audio"; > + audio-cpu = <&sai3>; > + audio-codec = <&wm8962>; > + audio-routing = > + "Headphone Jack", "HPOUTL", > + "Headphone Jack", "HPOUTR", > + "Ext Spk", "SPKOUTL", > + "Ext Spk", "SPKOUTR", > + "AMIC", "MICBIAS", > + "IN3R", "AMIC"; > + }; > +}; > + > +&ecspi2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_espi2>; > + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; > + status = "okay"; > + > + eeprom@0 { > + compatible = "microchip,at25160bn", "atmel,at25"; > + reg = <0>; > + spi-max-frequency = <5000000>; > + spi-cpha; > + spi-cpol; > + pagesize = <32>; > + size = <2048>; > + address-width = <16>; > + }; > +}; > + > +&i2c2 { > + clock-frequency = <400000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c2>; > + status = "okay"; Can you document why you keep empty bus enabled? > +}; > + > +&i2c4 { > + clock-frequency = <400000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c4>; > + status = "okay"; > + > + pca6416_0: gpio@20 { > + compatible = "nxp,pcal6416"; > + reg = <0x20>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pcal6414>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-parent = <&gpio4>; > + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; > + }; > + > + pca6416_1: gpio@21 { > + compatible = "nxp,pcal6416"; > + reg = <0x21>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-parent = <&gpio4>; > + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; > + }; > + > + wm8962: audio-codec@1a { > + compatible = "wlf,wm8962"; > + reg = <0x1a>; > + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; > + clock-names = "xclk"; > + DCVDD-supply = <®_audio>; > + DBVDD-supply = <®_audio>; > + AVDD-supply = <®_audio>; > + CPVDD-supply = <®_audio>; > + MICVDD-supply = <®_audio>; > + PLLVDD-supply = <®_audio>; > + SPKVDD1-supply = <®_audio>; > + SPKVDD2-supply = <®_audio>; > + gpio-cfg = < > + 0x0000 /* 0:Default */ > + 0x0000 /* 1:Default */ > + 0x0000 /* 2:FN_DMICCLK */ > + 0x0000 /* 3:Default */ > + 0x0000 /* 4:FN_DMICCDAT */ > + 0x0000 /* 5:Default */ > + >; > + }; > +}; > + > +&easrc { > + fsl,asrc-rate = <48000>; > + status = "okay"; > +}; > + > +&sai3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_sai3>; > + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; > + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; > + assigned-clock-rates = <24576000>; > + fsl,sai-mclk-direction-output; > + status = "okay"; > +}; > + > +&snvs_pwrkey { > + status = "okay"; > +}; > + > +&uart2 { /* console */ > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart2>; > + status = "okay"; > +}; > + > +&uart3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart3>; > + assigned-clocks = <&clk IMX8MN_CLK_UART3>; > + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; > + status = "okay"; > +}; > + > +&usbotg1 { > + vbus-supply = <®_usb_otg_vbus>; > + disable-over-current; > + dr_mode="otg"; > + status = "okay"; > +}; > + > +&usdhc2 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; > + bus-width = <4>; > + vmmc-supply = <®_usdhc2_vmmc>; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl_espi2: espi2grp { > + fsl,pins = < > + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 > + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 > + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 > + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 > + >; > + }; > + > + pinctrl_i2c2: i2c2grp { > + fsl,pins = < > + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 > + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 > + >; > + }; > + > + pinctrl_i2c4: i2c4grp { > + fsl,pins = < > + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 > + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 > + >; > + }; > + > + pinctrl_led3: led3grp { > + fsl,pins = < > + MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 > + >; > + }; > + > + pinctrl_pcal6414: pcal6414-gpiogrp { > + fsl,pins = < > + MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 > + >; > + }; > + > + pinctrl_reg_usb_otg: reg-otggrp { > + fsl,pins = < > + MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 > + >; > + }; > + > + pinctrl_sai3: sai3grp { > + fsl,pins = < > + MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 > + MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 > + MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 > + MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 > + MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 > + >; > + }; > + > + pinctrl_uart2: uart2grp { > + fsl,pins = < > + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 > + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 > + >; > + }; > + > + pinctrl_uart3: uart3grp { > + fsl,pins = < > + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 > + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 > + >; > + }; > + > + pinctrl_usdhc2_gpio: usdhc2gpiogrp { > + fsl,pins = < > + MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 > + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 > + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 > + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 > + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 > + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 > + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 > + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 > + >; > + }; > + > + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { > + fsl,pins = < > + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 > + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 > + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 > + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 > + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 > + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 > + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 > + >; > + }; > + > + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { > + fsl,pins = < > + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 > + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 > + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 > + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 > + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 > + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 > + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 > + >; > + }; > +}; > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts > new file mode 100644 > index 000000000000..faa55d888065 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts > @@ -0,0 +1,19 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright 2020 Compass Electronics Group, LLC > + */ > + > +/dts-v1/; > + > +#include "imx8mn.dtsi" > +#include "imx8mn-beacon-som.dtsi" > +#include "imx8mn-beacon-baseboard.dtsi" Why do you need baseboard as DTSI? Is is separate than kit? Judging by contents look like just empty/fake DTS and the baseboard should be the DTS. Another hint: Baseboard also does not have its compatible, so it cannot exist in real life separate from the development kit... > + > +/ { > + model = "Beacon EmbeddedWorks i.MX8M Mini Development Kit"; > + compatible = "beacon,imx8mn-beacon-kit", "fsl,imx8mn"; Undocumented compatible. > + > + chosen { > + stdout-path = &uart2; > + }; > +}; > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi > new file mode 100644 > index 000000000000..a2ce036b37f3 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi > @@ -0,0 +1,429 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright 2020 Compass Electronics Group, LLC > + */ > + > +/ { > + usdhc1_pwrseq: usdhc1_pwrseq { > + compatible = "mmc-pwrseq-simple"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usdhc1_gpio>; > + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; > + clocks = <&osc_32k>; > + clock-names = "ext_clock"; > + post-power-on-delay-ms = <80>; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0x0 0x40000000 0 0x80000000>; > + }; > +}; > + > +&A53_0 { > + cpu-supply = <&buck2_reg>; > +}; > + > +&A53_1 { > + cpu-supply = <&buck2_reg>; > +}; > + > +&A53_2 { > + cpu-supply = <&buck2_reg>; > +}; > + > +&A53_3 { > + cpu-supply = <&buck2_reg>; > +}; Empty line please. Best regards, Krzysztof
On Fri, Oct 23, 2020 at 4:44 AM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On Thu, Oct 22, 2020 at 11:57:50AM -0500, Adam Ford wrote: > > Beacon Embeddedworks is launching a development kit based on the > > i.MX8M Nano SoC. The kit consists of a System on Module (SOM) > > + baseboard. The SOM has the SoC, eMMC, and Ethernet. The baseboard > > has an wm8962 audio CODEC, and a single USB OTG. > > > > Signed-off-by: Adam Ford <aford173@gmail.com> > > --- > > Based on top of previous series found: > > https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=366931 > > > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > > index c7890b622587..ab47b3b1de75 100644 > > --- a/arch/arm64/boot/dts/freescale/Makefile > > +++ b/arch/arm64/boot/dts/freescale/Makefile > > @@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb > > +dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi > > new file mode 100644 > > index 000000000000..898715aa79b5 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi > > @@ -0,0 +1,313 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* > > + * Copyright 2020 Compass Electronics Group, LLC > > + */ > > + > > +/ { > > + leds { > > + compatible = "gpio-leds"; > > + > > + led0 { > > led-0 > > > + label = "gen_led0"; > > + gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; > > + default-state = "off"; > > + }; > > + > > + led1 { > > + label = "gen_led1"; > > + gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; > > + default-state = "off"; > > + }; > > + > > + led2 { > > + label = "gen_led2"; > > + gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; > > + default-state = "off"; > > + }; > > + > > + led3 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_led3>; > > + label = "heartbeat"; > > + gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; > > + linux,default-trigger = "heartbeat"; > > + }; > > + }; > > + > > + reg_audio: regulator-audio { > > + compatible = "regulator-fixed"; > > + regulator-name = "3v3_aud"; > > + regulator-min-microvolt = <3300000>; > > + regulator-max-microvolt = <3300000>; > > + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; > > + enable-active-high; > > + }; > > + > > + reg_usdhc2_vmmc: regulator-usdhc2 { > > + compatible = "regulator-fixed"; > > + regulator-name = "VSD_3V3"; > > lowercase name please to match everything else. OK. > > > + regulator-min-microvolt = <3300000>; > > + regulator-max-microvolt = <3300000>; > > + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; > > + enable-active-high; > > + }; > > + > > + reg_usb_otg_vbus: regulator-usb { > > + compatible = "regulator-fixed"; > > + pinctrl-0 = <&pinctrl_reg_usb_otg>; > > pinctrl-names... and test whether it really works after this change. > Without it the pinctrl was probably not applied. Good catch. I've been tracking some flakey USB support, and this may explain it. > > > + regulator-name = "usb_otg_vbus"; > > + regulator-min-microvolt = <5000000>; > > + regulator-max-microvolt = <5000000>; > > + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; > > + enable-active-high; > > + }; > > + > > + sound { > > + compatible = "fsl,imx-audio-wm8962"; > > + model = "wm8962-audio"; > > + audio-cpu = <&sai3>; > > + audio-codec = <&wm8962>; > > + audio-routing = > > + "Headphone Jack", "HPOUTL", > > + "Headphone Jack", "HPOUTR", > > + "Ext Spk", "SPKOUTL", > > + "Ext Spk", "SPKOUTR", > > + "AMIC", "MICBIAS", > > + "IN3R", "AMIC"; > > + }; > > +}; > > + > > +&ecspi2 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_espi2>; > > + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; > > + status = "okay"; > > + > > + eeprom@0 { > > + compatible = "microchip,at25160bn", "atmel,at25"; > > + reg = <0>; > > + spi-max-frequency = <5000000>; > > + spi-cpha; > > + spi-cpol; > > + pagesize = <32>; > > + size = <2048>; > > + address-width = <16>; > > + }; > > +}; > > + > > +&i2c2 { > > + clock-frequency = <400000>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_i2c2>; > > + status = "okay"; > > Can you document why you keep empty bus enabled? I can disable it for now. It will eventually house a CSI camera once the CSI interface is available. > > > +}; > > + > > +&i2c4 { > > + clock-frequency = <400000>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_i2c4>; > > + status = "okay"; > > + > > + pca6416_0: gpio@20 { > > + compatible = "nxp,pcal6416"; > > + reg = <0x20>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_pcal6414>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupt-parent = <&gpio4>; > > + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; > > + }; > > + > > + pca6416_1: gpio@21 { > > + compatible = "nxp,pcal6416"; > > + reg = <0x21>; > > + gpio-controller; > > + #gpio-cells = <2>; > > + interrupt-parent = <&gpio4>; > > + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; > > + }; > > + > > + wm8962: audio-codec@1a { > > + compatible = "wlf,wm8962"; > > + reg = <0x1a>; > > + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; > > + clock-names = "xclk"; > > + DCVDD-supply = <®_audio>; > > + DBVDD-supply = <®_audio>; > > + AVDD-supply = <®_audio>; > > + CPVDD-supply = <®_audio>; > > + MICVDD-supply = <®_audio>; > > + PLLVDD-supply = <®_audio>; > > + SPKVDD1-supply = <®_audio>; > > + SPKVDD2-supply = <®_audio>; > > + gpio-cfg = < > > + 0x0000 /* 0:Default */ > > + 0x0000 /* 1:Default */ > > + 0x0000 /* 2:FN_DMICCLK */ > > + 0x0000 /* 3:Default */ > > + 0x0000 /* 4:FN_DMICCDAT */ > > + 0x0000 /* 5:Default */ > > + >; > > + }; > > +}; > > + > > +&easrc { > > + fsl,asrc-rate = <48000>; > > + status = "okay"; > > +}; > > + > > +&sai3 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_sai3>; > > + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; > > + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; > > + assigned-clock-rates = <24576000>; > > + fsl,sai-mclk-direction-output; > > + status = "okay"; > > +}; > > + > > +&snvs_pwrkey { > > + status = "okay"; > > +}; > > + > > +&uart2 { /* console */ > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_uart2>; > > + status = "okay"; > > +}; > > + > > +&uart3 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_uart3>; > > + assigned-clocks = <&clk IMX8MN_CLK_UART3>; > > + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; > > + status = "okay"; > > +}; > > + > > +&usbotg1 { > > + vbus-supply = <®_usb_otg_vbus>; > > + disable-over-current; > > + dr_mode="otg"; > > + status = "okay"; > > +}; > > + > > +&usdhc2 { > > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; > > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; > > + bus-width = <4>; > > + vmmc-supply = <®_usdhc2_vmmc>; > > + status = "okay"; > > +}; > > + > > +&iomuxc { > > + pinctrl_espi2: espi2grp { > > + fsl,pins = < > > + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 > > + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 > > + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 > > + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 > > + >; > > + }; > > + > > + pinctrl_i2c2: i2c2grp { > > + fsl,pins = < > > + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 > > + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 > > + >; > > + }; > > + > > + pinctrl_i2c4: i2c4grp { > > + fsl,pins = < > > + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 > > + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 > > + >; > > + }; > > + > > + pinctrl_led3: led3grp { > > + fsl,pins = < > > + MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 > > + >; > > + }; > > + > > + pinctrl_pcal6414: pcal6414-gpiogrp { > > + fsl,pins = < > > + MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 > > + >; > > + }; > > + > > + pinctrl_reg_usb_otg: reg-otggrp { > > + fsl,pins = < > > + MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 > > + >; > > + }; > > + > > + pinctrl_sai3: sai3grp { > > + fsl,pins = < > > + MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 > > + MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 > > + MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 > > + MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 > > + MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 > > + >; > > + }; > > + > > + pinctrl_uart2: uart2grp { > > + fsl,pins = < > > + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 > > + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 > > + >; > > + }; > > + > > + pinctrl_uart3: uart3grp { > > + fsl,pins = < > > + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 > > + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 > > + >; > > + }; > > + > > + pinctrl_usdhc2_gpio: usdhc2gpiogrp { > > + fsl,pins = < > > + MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 > > + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 > > + >; > > + }; > > + > > + pinctrl_usdhc2: usdhc2grp { > > + fsl,pins = < > > + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 > > + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 > > + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 > > + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 > > + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 > > + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 > > + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 > > + >; > > + }; > > + > > + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { > > + fsl,pins = < > > + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 > > + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 > > + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 > > + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 > > + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 > > + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 > > + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 > > + >; > > + }; > > + > > + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { > > + fsl,pins = < > > + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 > > + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 > > + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 > > + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 > > + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 > > + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 > > + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 > > + >; > > + }; > > +}; > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts > > new file mode 100644 > > index 000000000000..faa55d888065 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts > > @@ -0,0 +1,19 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* > > + * Copyright 2020 Compass Electronics Group, LLC > > + */ > > + > > +/dts-v1/; > > + > > +#include "imx8mn.dtsi" > > +#include "imx8mn-beacon-som.dtsi" > > +#include "imx8mn-beacon-baseboard.dtsi" > > Why do you need baseboard as DTSI? Is is separate than kit? Judging by > contents look like just empty/fake DTS and the baseboard should be the > DTS. > > Another hint: Baseboard also does not have its compatible, so it cannot > exist in real life separate from the development kit... The baseboard can handle two separate, mutually exclusive video outputs. It has a LVDS bridge chip and an HDMI bridge chip, but without the DSI and LCDIF support, neither can function. Right now, that LVDS chip doesn't have an upstream driver, but I plan to introduce it once the LCDIF, and DSI interfaces are available and functional. Once there is video support, the kit-level DTS file will get support for one of the video outputs, and a second DTS file will get created to support the other. Both of these kit-level files would include the baseboard and SOM DTSI files since they would be common to both kits. > > + > > +/ { > > + model = "Beacon EmbeddedWorks i.MX8M Mini Development Kit"; > > + compatible = "beacon,imx8mn-beacon-kit", "fsl,imx8mn"; > > Undocumented compatible. I am still trying to learn the YAML rules. Do I just add it to the fsl.yaml? 'beacon' is in the vendor-prefixes, but I looked and the 'imx8mm-beacon-kit' which is already in the kernel doesn't have a compatible either and they are virtually identical. > > > + > > + chosen { > > + stdout-path = &uart2; > > + }; > > +}; > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi > > new file mode 100644 > > index 000000000000..a2ce036b37f3 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi > > @@ -0,0 +1,429 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* > > + * Copyright 2020 Compass Electronics Group, LLC > > + */ > > + > > +/ { > > + usdhc1_pwrseq: usdhc1_pwrseq { > > + compatible = "mmc-pwrseq-simple"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_usdhc1_gpio>; > > + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; > > + clocks = <&osc_32k>; > > + clock-names = "ext_clock"; > > + post-power-on-delay-ms = <80>; > > + }; > > + > > + memory@40000000 { > > + device_type = "memory"; > > + reg = <0x0 0x40000000 0 0x80000000>; > > + }; > > +}; > > + > > +&A53_0 { > > + cpu-supply = <&buck2_reg>; > > +}; > > + > > +&A53_1 { > > + cpu-supply = <&buck2_reg>; > > +}; > > + > > +&A53_2 { > > + cpu-supply = <&buck2_reg>; > > +}; > > + > > +&A53_3 { > > + cpu-supply = <&buck2_reg>; > > +}; > > Empty line please. I'll submit a V2 with the changes you requested > > Best regards, > Krzysztof
On Fri, Oct 23, 2020 at 05:51:56AM -0500, Adam Ford wrote: > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts > > > new file mode 100644 > > > index 000000000000..faa55d888065 > > > --- /dev/null > > > +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts > > > @@ -0,0 +1,19 @@ > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > > +/* > > > + * Copyright 2020 Compass Electronics Group, LLC > > > + */ > > > + > > > +/dts-v1/; > > > + > > > +#include "imx8mn.dtsi" > > > +#include "imx8mn-beacon-som.dtsi" > > > +#include "imx8mn-beacon-baseboard.dtsi" > > > > Why do you need baseboard as DTSI? Is is separate than kit? Judging by > > contents look like just empty/fake DTS and the baseboard should be the > > DTS. > > > > Another hint: Baseboard also does not have its compatible, so it cannot > > exist in real life separate from the development kit... > > The baseboard can handle two separate, mutually exclusive video > outputs. It has a LVDS bridge chip and an HDMI bridge chip, but > without the DSI and LCDIF support, neither can function. > Right now, that LVDS chip doesn't have an upstream driver, but I plan > to introduce it once the LCDIF, and DSI interfaces are available and > functional. > > Once there is video support, the kit-level DTS file will get support > for one of the video outputs, and a second DTS file will get created > to support the other. Both of these kit-level files would include the > baseboard and SOM DTSI files since they would be common to both kits. Sounds good. > > > > + > > > +/ { > > > + model = "Beacon EmbeddedWorks i.MX8M Mini Development Kit"; > > > + compatible = "beacon,imx8mn-beacon-kit", "fsl,imx8mn"; > > > > Undocumented compatible. > > I am still trying to learn the YAML rules. Do I just add it to the > fsl.yaml? 'beacon' is in the vendor-prefixes, but I looked and the > 'imx8mm-beacon-kit' which is already in the kernel doesn't have a > compatible either and they are virtually identical. Enough will be adding it to the fsl.yaml. There is no strict need for separate compatible for baseboard, although that's quite common practice since you want to reuse it. The beacon,imx8mm-beacon-kit is in fsl.yaml, so you can just duplicate for imx8mn. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index c7890b622587..ab47b3b1de75 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi new file mode 100644 index 000000000000..898715aa79b5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +/ { + leds { + compatible = "gpio-leds"; + + led0 { + label = "gen_led0"; + gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led1 { + label = "gen_led1"; + gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led2 { + label = "gen_led2"; + gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led3>; + label = "heartbeat"; + gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_audio: regulator-audio { + compatible = "regulator-fixed"; + regulator-name = "3v3_aud"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usb { + compatible = "regulator-fixed"; + pinctrl-0 = <&pinctrl_reg_usb_otg>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_espi2>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + eeprom@0 { + compatible = "microchip,at25160bn", "atmel,at25"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-cpha; + spi-cpol; + pagesize = <32>; + size = <2048>; + address-width = <16>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + pca6416_0: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6414>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + pca6416_1: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + wm8962: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; + clock-names = "xclk"; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MN_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg_vbus>; + disable-over-current; + dr_mode="otg"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_espi2: espi2grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_led3: led3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 + >; + }; + + pinctrl_pcal6414: pcal6414-gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 + >; + }; + + pinctrl_reg_usb_otg: reg-otggrp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts new file mode 100644 index 000000000000..faa55d888065 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +/dts-v1/; + +#include "imx8mn.dtsi" +#include "imx8mn-beacon-som.dtsi" +#include "imx8mn-beacon-baseboard.dtsi" + +/ { + model = "Beacon EmbeddedWorks i.MX8M Mini Development Kit"; + compatible = "beacon,imx8mn-beacon-kit", "fsl,imx8mn"; + + chosen { + stdout-path = &uart2; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi new file mode 100644 index 000000000000..a2ce036b37f3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +/ { + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_gpio>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + clocks = <&osc_32k>; + clock-names = "ext_clock"; + post-power-on-delay-ms = <80>; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; +/* DDR controller is running LPDDR at 800MHz which requires 0.95V */ +&a53_opp_table { + opp-1200000000 { + opp-microvolt = <950000>; + }; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "buck4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + eeprom@50 { + compatible = "microchip,24c64", "atmel,24c64"; + pagesize = <32>; + read-only; /* Manufacturing EEPROM programmed at factory */ + reg = <0x50>; + }; + + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + clocks = <&osc_32k>; + clock-names = "extclk"; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + non-removable; + cap-power-off-card; + pm-ignore-notify; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc1_pwrseq>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 + MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 + MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; +};
Beacon Embeddedworks is launching a development kit based on the i.MX8M Nano SoC. The kit consists of a System on Module (SOM) + baseboard. The SOM has the SoC, eMMC, and Ethernet. The baseboard has an wm8962 audio CODEC, and a single USB OTG. Signed-off-by: Adam Ford <aford173@gmail.com> --- Based on top of previous series found: https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=366931