[v3,00/35] Fix x2apic enablement and allow more CPUs, clean up I/OAPIC and MSI bitfields

Message ID	20201024213535.443185-1-dwmw2@infradead.org (mailing list archive)
Headers	show Return-Path: <SRS0=sCQZ=D7=vger.kernel.org=kvm-owner@kernel.org> From: David Woodhouse <dwmw2@infradead.org> To: x86@kernel.org Cc: kvm <kvm@vger.kernel.org>, iommu@lists.linux-foundation.org, joro@8bytes.org, Thomas Gleixner <tglx@linutronix.de>, Paolo Bonzini <pbonzini@redhat.com>, linux-kernel <linux-kernel@vger.kernel.org>, linux-hyperv@vger.kernel.org, maz@misterjones.org, Dexuan Cui <decui@microsoft.com> Subject: [PATCH v3 00/35] Fix x2apic enablement and allow more CPUs, clean up I/OAPIC and MSI bitfields Date: Sat, 24 Oct 2020 22:35:00 +0100 Message-Id: <20201024213535.443185-1-dwmw2@infradead.org> In-Reply-To: <e6601ff691afb3266e365a91e8b221179daf22c2.camel@infradead.org> References: <e6601ff691afb3266e365a91e8b221179daf22c2.camel@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: David Woodhouse <dwmw2@infradead.org> Precedence: bulk
Series	Fix x2apic enablement and allow more CPUs, clean up I/OAPIC and MSI bitfields \| expand [v3,00/35] Fix x2apic enablement and allow more CPUs, clean up I/OAPIC and MSI bitfields [v3,01/35] x86/apic: Fix x2apic enablement without interrupt remapping [v3,02/35] x86/msi: Only use high bits of MSI address for DMAR unit [v3,03/35] x86/apic/uv: Fix inconsistent destination mode [v3,04/35] x86/devicetree: Fix the ioapic interrupt type table [v3,05/35] x86/apic: Cleanup delivery mode defines [v3,06/35] x86/apic: Replace pointless apic::dest_logical usage [v3,07/35] x86/apic: Get rid of apic::dest_logical [v3,08/35] x86/apic: Cleanup destination mode [v3,09/35] x86/apic: Always provide irq_compose_msi_msg() method for vector domain [v3,10/35] x86/hpet: Move MSI support into hpet.c [v3,11/35] genirq/msi: Allow shadow declarations of msi_msg::$member [v3,12/35] x86/msi: Provide msi message shadow structs [v3,13/35] iommu/intel: Use msi_msg shadow structs [v3,14/35] iommu/amd: Use msi_msg shadow structs [v3,15/35] PCI: vmd: Use msi_msg shadow structs [v3,16/35] x86/kvm: Use msi_msg shadow structs [v3,17/35] x86/pci/xen: Use msi_msg shadow structs [v3,18/35] x86/msi: Remove msidef.h [v3,19/35] x86/io_apic: Cleanup trigger/polarity helpers [v3,20/35] x86/ioapic: Cleanup IO/APIC route entry structs [v3,21/35] x86/ioapic: Generate RTE directly from parent irqchip's MSI message [v3,22/35] genirq/irqdomain: Implement get_name() method on irqchip fwnodes [v3,23/35] x86/apic: Add select() method on vector irqdomain [v3,24/35] iommu/amd: Implement select() method on remapping irqdomain [v3,25/35] iommu/vt-d: Implement select() method on remapping irqdomain [v3,26/35] iommu/hyper-v: Implement select() method on remapping irqdomain [v3,27/35] x86/hpet: Use irq_find_matching_fwspec() to find remapping irqdomain [v3,28/35] x86/ioapic: Use irq_find_matching_fwspec() to find remapping irqdomain [v3,29/35] x86: Kill all traces of irq_remapping_get_irq_domain() [v3,30/35] iommu/vt-d: Simplify intel_irq_remapping_select() [v3,31/35] x86/ioapic: Handle Extended Destination ID field in RTE [v3,32/35] x86/apic: Support 15 bits of APIC ID in MSI where available [v3,33/35] iommu/hyper-v: Disable IRQ pseudo-remapping if 15 bit APIC IDs are available [v3,34/35] x86/kvm: Reserve KVM_FEATURE_MSI_EXT_DEST_ID [v3,35/35] x86/kvm: Enable 15-bit extension when KVM_FEATURE_MSI_EXT_DEST_ID detected

Message ID

20201024213535.443185-1-dwmw2@infradead.org (mailing list archive)

Headers

From: David Woodhouse <dwmw2@infradead.org>
To: x86@kernel.org
Cc: kvm <kvm@vger.kernel.org>, iommu@lists.linux-foundation.org,
        joro@8bytes.org, Thomas Gleixner <tglx@linutronix.de>,
        Paolo Bonzini <pbonzini@redhat.com>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        linux-hyperv@vger.kernel.org, maz@misterjones.org,
        Dexuan Cui <decui@microsoft.com>
Subject: [PATCH v3 00/35] Fix x2apic enablement and allow more CPUs,
 clean up I/OAPIC and MSI bitfields
Date: Sat, 24 Oct 2020 22:35:00 +0100
Message-Id: <20201024213535.443185-1-dwmw2@infradead.org>
In-Reply-To: <e6601ff691afb3266e365a91e8b221179daf22c2.camel@infradead.org>
References: <e6601ff691afb3266e365a91e8b221179daf22c2.camel@infradead.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Sender: David Woodhouse <dwmw2@infradead.org>
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Series

Fix x2apic enablement and allow more CPUs, clean up I/OAPIC and MSI bitfields | expand

Message

David Woodhouse Oct. 24, 2020, 9:35 p.m. UTC

Fix the conditions for enabling x2apic on guests without interrupt 
remapping, and support 15-bit Extended Destination ID to allow 32768 
CPUs without IR on hypervisors that support it.

Make the I/OAPIC code generate its RTE directly from the MSI message
created by the parent irqchip, and fix up a bunch of magic mask/shift
macros to use bitfields for MSI messages and I/OAPIC RTEs while we're
at it.

v3:
 • Lots of bitfield cleanups from Thomas.
 • Disable hyperv-iommu if 15-bit extension is present.
 • Fix inconsistent CONFIG_PCI_MSI/CONFIG_GENERIC_MSI_IRQ in hpet.c
 • Split KVM_FEATURE_MSI_EXT_DEST_ID patch, half of which is going upstream
   through KVM tree (and the other half needs to wait, or have an #ifdef) so
   is left at the top of the tree.

v2:
 • Minor cleanups.
 • Move __irq_msi_compose_msg() to apic.c, make virt_ext_dest_id static.
 • Generate I/OAPIC RTE directly from parent irqchip's MSI messages.
 • Clean up HPET MSI support into hpet.c now that we can.

David Woodhouse (19):
      x86/apic: Fix x2apic enablement without interrupt remapping
      x86/msi: Only use high bits of MSI address for DMAR unit
      x86/apic: Always provide irq_compose_msi_msg() method for vector domain
      x86/hpet: Move MSI support into hpet.c
      x86/ioapic: Generate RTE directly from parent irqchip's MSI message
      genirq/irqdomain: Implement get_name() method on irqchip fwnodes
      x86/apic: Add select() method on vector irqdomain
      iommu/amd: Implement select() method on remapping irqdomain
      iommu/vt-d: Implement select() method on remapping irqdomain
      iommu/hyper-v: Implement select() method on remapping irqdomain
      x86/hpet: Use irq_find_matching_fwspec() to find remapping irqdomain
      x86/ioapic: Use irq_find_matching_fwspec() to find remapping irqdomain
      x86: Kill all traces of irq_remapping_get_irq_domain()
      iommu/vt-d: Simplify intel_irq_remapping_select()
      x86/ioapic: Handle Extended Destination ID field in RTE
      x86/apic: Support 15 bits of APIC ID in MSI where available
      iommu/hyper-v: Disable IRQ pseudo-remapping if 15 bit APIC IDs are available
      x86/kvm: Reserve KVM_FEATURE_MSI_EXT_DEST_ID
      x86/kvm: Enable 15-bit extension when KVM_FEATURE_MSI_EXT_DEST_ID detected

Thomas Gleixner (16):
      x86/apic/uv: Fix inconsistent destination mode
      x86/devicetree: Fix the ioapic interrupt type table
      x86/apic: Cleanup delivery mode defines
      x86/apic: Replace pointless apic::dest_logical usage
      x86/apic: Get rid of apic::dest_logical
      x86/apic: Cleanup destination mode
      genirq/msi: Allow shadow declarations of msi_msg::$member
      x86/msi: Provide msi message shadow structs
      iommu/intel: Use msi_msg shadow structs
      iommu/amd: Use msi_msg shadow structs
      PCI: vmd: Use msi_msg shadow structs
      x86/kvm: Use msi_msg shadow structs
      x86/pci/xen: Use msi_msg shadow structs
      x86/msi: Remove msidef.h
      x86/io_apic: Cleanup trigger/polarity helpers
      x86/ioapic: Cleanup IO/APIC route entry structs

 Documentation/virt/kvm/cpuid.rst      |   4 +
 arch/x86/include/asm/apic.h           |  16 +-
 arch/x86/include/asm/apicdef.h        |  16 +-
 arch/x86/include/asm/hpet.h           |  11 -
 arch/x86/include/asm/hw_irq.h         |  13 +-
 arch/x86/include/asm/io_apic.h        |  79 ++----
 arch/x86/include/asm/irq_remapping.h  |   9 -
 arch/x86/include/asm/irqdomain.h      |   3 +
 arch/x86/include/asm/msi.h            |  50 ++++
 arch/x86/include/asm/msidef.h         |  57 ----
 arch/x86/include/asm/x86_init.h       |   2 +
 arch/x86/include/uapi/asm/kvm_para.h  |   1 +
 arch/x86/kernel/apic/apic.c           |  73 ++++-
 arch/x86/kernel/apic/apic_flat_64.c   |  18 +-
 arch/x86/kernel/apic/apic_noop.c      |  10 +-
 arch/x86/kernel/apic/apic_numachip.c  |  16 +-
 arch/x86/kernel/apic/bigsmp_32.c      |   9 +-
 arch/x86/kernel/apic/io_apic.c        | 503 ++++++++++++++++++----------------
 arch/x86/kernel/apic/ipi.c            |   6 +-
 arch/x86/kernel/apic/msi.c            | 153 +----------
 arch/x86/kernel/apic/probe_32.c       |   9 +-
 arch/x86/kernel/apic/vector.c         |  49 ++++
 arch/x86/kernel/apic/x2apic_cluster.c |  10 +-
 arch/x86/kernel/apic/x2apic_phys.c    |  17 +-
 arch/x86/kernel/apic/x2apic_uv_x.c    |  12 +-
 arch/x86/kernel/devicetree.c          |  30 +-
 arch/x86/kernel/hpet.c                | 122 ++++++++-
 arch/x86/kernel/kvm.c                 |   6 +
 arch/x86/kernel/smpboot.c             |   8 +-
 arch/x86/kernel/x86_init.c            |   1 +
 arch/x86/kvm/irq_comm.c               |  31 +--
 arch/x86/pci/intel_mid_pci.c          |   8 +-
 arch/x86/pci/xen.c                    |  26 +-
 arch/x86/platform/uv/uv_irq.c         |   4 +-
 arch/x86/xen/apic.c                   |   7 +-
 drivers/iommu/amd/amd_iommu_types.h   |   2 +-
 drivers/iommu/amd/init.c              |  46 ++--
 drivers/iommu/amd/iommu.c             |  93 +++----
 drivers/iommu/hyperv-iommu.c          |  44 +--
 drivers/iommu/intel/irq_remapping.c   | 102 +++----
 drivers/iommu/irq_remapping.c         |  14 -
 drivers/iommu/irq_remapping.h         |   3 -
 drivers/pci/controller/pci-hyperv.c   |   6 +-
 drivers/pci/controller/vmd.c          |   9 +-
 include/asm-generic/msi.h             |   4 +
 include/linux/msi.h                   |  46 +++-
 kernel/irq/irqdomain.c                |  11 +-
 47 files changed, 890 insertions(+), 879 deletions(-)

Comments

David Woodhouse Oct. 25, 2020, 8:12 a.m. UTC | #1

On Sat, 2020-10-24 at 22:35 +0100, David Woodhouse wrote:
> Fix the conditions for enabling x2apic on guests without interrupt 
> remapping, and support 15-bit Extended Destination ID to allow 32768 
> CPUs without IR on hypervisors that support it.
> 
> Make the I/OAPIC code generate its RTE directly from the MSI message
> created by the parent irqchip, and fix up a bunch of magic mask/shift
> macros to use bitfields for MSI messages and I/OAPIC RTEs while we're
> at it.

Forgot to mention (since I thought I'd posted it in a previous series)
that v3 also ditches irq_remapping_get_irq_domain() and some icky
special cases of hard-coding "x86_vector_domain", and makes HPET and
I/OAPIC use irq_find_matching_fwspeC() to find their parent irqdomain.

> v3:
>  • Lots of bitfield cleanups from Thomas.
>  • Disable hyperv-iommu if 15-bit extension is present.
>  • Fix inconsistent CONFIG_PCI_MSI/CONFIG_GENERIC_MSI_IRQ in hpet.c
>  • Split KVM_FEATURE_MSI_EXT_DEST_ID patch, half of which is going upstream
>    through KVM tree (and the other half needs to wait, or have an #ifdef) so
>    is left at the top of the tree.
> 
> v2:
>  • Minor cleanups.
>  • Move __irq_msi_compose_msg() to apic.c, make virt_ext_dest_id static.
>  • Generate I/OAPIC RTE directly from parent irqchip's MSI messages.
>  • Clean up HPET MSI support into hpet.c now that we can.