| Message ID | 20201104232218.198800-5-konrad.dybcio@somainline.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add KRYO2XX Errata / mitigations data | expand |
On 2020-11-04 23:22, Konrad Dybcio wrote: > QCOM KRYO2XX Silver cores are Cortex-A53 based and are > susceptible to the 845719 erratum. Add them to the lookup > list to apply the erratum. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> > --- > arch/arm64/kernel/cpu_errata.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/kernel/cpu_errata.c > b/arch/arm64/kernel/cpu_errata.c > index 61314fd70f13..cafaf0da05b7 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -299,6 +299,8 @@ static const struct midr_range > erratum_845719_list[] = { > MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), > /* Brahma-B53 r0p[0] */ > MIDR_REV(MIDR_BRAHMA_B53, 0, 0), > + /* Kryo2XX Silver rAp4 */ > + MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4), Is this the only affected version? If this is actually an A53, how do the revisions map between Kryo and Cortex cores? M.
> Is this the only affected version? If this is actually an A53, how do the > revisions map between Kryo and Cortex cores? Hi, sadly, I do not have access to such information. Only this specific revision has been marked as affected in the BSP kernel. Konrad
Hi Marc, On 2020-11-05 14:59, Marc Zyngier wrote: > On 2020-11-04 23:22, Konrad Dybcio wrote: >> QCOM KRYO2XX Silver cores are Cortex-A53 based and are >> susceptible to the 845719 erratum. Add them to the lookup >> list to apply the erratum. >> >> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> >> --- >> arch/arm64/kernel/cpu_errata.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/arch/arm64/kernel/cpu_errata.c >> b/arch/arm64/kernel/cpu_errata.c >> index 61314fd70f13..cafaf0da05b7 100644 >> --- a/arch/arm64/kernel/cpu_errata.c >> +++ b/arch/arm64/kernel/cpu_errata.c >> @@ -299,6 +299,8 @@ static const struct midr_range >> erratum_845719_list[] = { >> MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), >> /* Brahma-B53 r0p[0] */ >> MIDR_REV(MIDR_BRAHMA_B53, 0, 0), >> + /* Kryo2XX Silver rAp4 */ >> + MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4), > > Is this the only affected version? If this is actually an A53, how do > the > revisions map between Kryo and Cortex cores? > From what I see from the docs, this is the only version used in MSM8998(silver cores are based on Cortex A53) and it maps to r0p4. @Konrad, can you include (rap4 => r0p4) in comment. Thanks, Sai
> From what I see from the docs, this is the only version used > in MSM8998(silver cores are based on Cortex A53) and it maps > to r0p4. @Konrad, can you include (rap4 => r0p4) in comment. Hi, Thanks for looking into it. Could you perhaps check if it's also the case on sdm630/636/660? Konrad
Hi, On 2020-11-10 00:58, Konrad Dybcio wrote: >> From what I see from the docs, this is the only version used >> in MSM8998(silver cores are based on Cortex A53) and it maps >> to r0p4. @Konrad, can you include (rap4 => r0p4) in comment. > > > Hi, > > Thanks for looking into it. Could you perhaps check if it's also the > case on sdm630/636/660? > Yes I checked with CPU team now and its the same. Thanks, Sai
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 61314fd70f13..cafaf0da05b7 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -299,6 +299,8 @@ static const struct midr_range erratum_845719_list[] = { MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), /* Brahma-B53 r0p[0] */ MIDR_REV(MIDR_BRAHMA_B53, 0, 0), + /* Kryo2XX Silver rAp4 */ + MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4), {}, }; #endif
QCOM KRYO2XX Silver cores are Cortex-A53 based and are susceptible to the 845719 erratum. Add them to the lookup list to apply the erratum. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> --- arch/arm64/kernel/cpu_errata.c | 2 ++ 1 file changed, 2 insertions(+)