| Message ID | 20201116151735.178737-4-pgwipeout@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | rk3328 usb3 phy driver | expand |
Hi Peter, Just some comments... The compatible "rockchip,rk3328-dwc3" is currently under test in: https://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git/ I think we should let it go in mainline first (if the maintainers agree?) and then you can base your serie on that. The compatible "rockchip,rk3328-usb3phy" needs to be added to a document as well. Add increase version number after previous series. Is there any change in code or on how you detect? On 11/16/20 4:17 PM, Peter Geis wrote: > Add the usb3 controller and usb3 phy nodes to the rk3328. > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > --- > arch/arm64/boot/dts/rockchip/rk3328.dtsi | 65 ++++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > index bbdb19a3e85d..9fea9203d114 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > @@ -853,6 +853,40 @@ u2phy_host: host-port { > }; > }; > > + usb3phy: usb3-phy@ff470000 { > + compatible = "rockchip,rk3328-usb3phy"; > + reg = <0x0 0xff460000 0x0 0x10000>; > + clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; > + clock-names = "usb3phy-otg", "usb3phy-pipe"; > + resets = <&cru SRST_USB3PHY_U2>, > + <&cru SRST_USB3PHY_U3>, > + <&cru SRST_USB3PHY_PIPE>, > + <&cru SRST_USB3OTG_UTMI>, > + <&cru SRST_USB3PHY_OTG_P>, > + <&cru SRST_USB3PHY_PIPE_P>; > + reset-names = "usb3phy-u2-por", "usb3phy-u3-por", > + "usb3phy-pipe-mac", "usb3phy-utmi-mac", > + "usb3phy-utmi-apb", "usb3phy-pipe-apb"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; > + > + usb3phy_utmi: utmi@ff470000 { > + compatible = "rockchip,rk3328-usb3phy-utmi"; > + reg = <0x0 0xff470000 0x0 0x8000>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > + usb3phy_pipe: pipe@ff478000 { > + compatible = "rockchip,rk3328-usb3phy-pipe"; > + reg = <0x0 0xff478000 0x0 0x8000>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + }; > + > sdmmc: mmc@ff500000 { > compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; > reg = <0x0 0xff500000 0x0 0x4000>; > @@ -983,6 +1017,37 @@ usb_host0_ohci: usb@ff5d0000 { > status = "disabled"; > }; > > + usbdrd3: usb@ff600000 { > + compatible = "rockchip,rk3328-dwc3"; > + clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>, > + <&cru SCLK_USB3OTG_SUSPEND>; > + clock-names = "ref", "bus_early", "suspend"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; > + > + usbdrd_dwc3: dwc3@ff600000 { > + compatible = "snps,dwc3"; > + reg = <0x0 0xff600000 0x0 0x100000>; > + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>, > + <&cru SCLK_USB3OTG_SUSPEND>; > + clock-names = "ref", "bus_early", "suspend"; > + dr_mode = "host"; > + usb-phy = <&usb3phy_utmi>, <&usb3phy_pipe>; > + phy_type = "utmi_wide"; > + snps,dis_enblslpm_quirk; > + snps,dis-u2-freeclk-exists-quirk; > + snps,dis_u2_susphy_quirk; > + snps,dis_u3_susphy_quirk; > + snps,dis-del-phy-power-chg-quirk; > + snps,dis-tx-ipgap-linecheck-quirk; > + snps,xhci-trb-ent-quirk; > + status = "disabled"; > + }; > + }; > + > gic: interrupt-controller@ff811000 { > compatible = "arm,gic-400"; > #interrupt-cells = <3>; >
On Mon, Nov 16, 2020 at 11:07 AM Johan Jonker <jbx6244@gmail.com> wrote: > > Hi Peter, > > Just some comments... > > The compatible "rockchip,rk3328-dwc3" is currently under test in: > > https://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git/ > > I think we should let it go in mainline first > (if the maintainers agree?) and then you can base your serie on that. > > The compatible "rockchip,rk3328-usb3phy" needs to be added to a document > as well. I will address documentation in the complete patch set. This set to get feedback on the method of implementation and if possible make the glue layer unnecessary. > > Add increase version number after previous series. > > Is there any change in code or on how you detect? It would seem that the patches you just linked simply enable the usb3 controller. It does not address the original issues as to why this method was rejected previously. Without the phy driver, there is no hotplug detection, meaning that only devices which are plugged in at boot are enumerated. If you look at patch 2, you will see my glue driver is based off of-simple. This is no accident, as I had originally plugged in my code into that driver. At >40% rewrite of of-simple, it didn't feel "simple" anymore, so I broke it out separately. The patches you linked will work if the usb2 hub issue can be resolved purely in the phy driver. > > On 11/16/20 4:17 PM, Peter Geis wrote: > > Add the usb3 controller and usb3 phy nodes to the rk3328. > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > --- > > arch/arm64/boot/dts/rockchip/rk3328.dtsi | 65 ++++++++++++++++++++++++ > > 1 file changed, 65 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > > index bbdb19a3e85d..9fea9203d114 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > > @@ -853,6 +853,40 @@ u2phy_host: host-port { > > }; > > }; > > > > + usb3phy: usb3-phy@ff470000 { > > + compatible = "rockchip,rk3328-usb3phy"; > > + reg = <0x0 0xff460000 0x0 0x10000>; > > + clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; > > + clock-names = "usb3phy-otg", "usb3phy-pipe"; > > + resets = <&cru SRST_USB3PHY_U2>, > > + <&cru SRST_USB3PHY_U3>, > > + <&cru SRST_USB3PHY_PIPE>, > > + <&cru SRST_USB3OTG_UTMI>, > > + <&cru SRST_USB3PHY_OTG_P>, > > + <&cru SRST_USB3PHY_PIPE_P>; > > + reset-names = "usb3phy-u2-por", "usb3phy-u3-por", > > + "usb3phy-pipe-mac", "usb3phy-utmi-mac", > > + "usb3phy-utmi-apb", "usb3phy-pipe-apb"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + status = "disabled"; > > + > > + usb3phy_utmi: utmi@ff470000 { > > + compatible = "rockchip,rk3328-usb3phy-utmi"; > > + reg = <0x0 0xff470000 0x0 0x8000>; > > + #phy-cells = <0>; > > + status = "disabled"; > > + }; > > + > > + usb3phy_pipe: pipe@ff478000 { > > + compatible = "rockchip,rk3328-usb3phy-pipe"; > > + reg = <0x0 0xff478000 0x0 0x8000>; > > + #phy-cells = <0>; > > + status = "disabled"; > > + }; > > + }; > > + > > sdmmc: mmc@ff500000 { > > compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; > > reg = <0x0 0xff500000 0x0 0x4000>; > > @@ -983,6 +1017,37 @@ usb_host0_ohci: usb@ff5d0000 { > > status = "disabled"; > > }; > > > > + usbdrd3: usb@ff600000 { > > + compatible = "rockchip,rk3328-dwc3"; > > + clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>, > > + <&cru SCLK_USB3OTG_SUSPEND>; > > + clock-names = "ref", "bus_early", "suspend"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + status = "disabled"; > > + > > + usbdrd_dwc3: dwc3@ff600000 { > > + compatible = "snps,dwc3"; > > + reg = <0x0 0xff600000 0x0 0x100000>; > > + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>, > > + <&cru SCLK_USB3OTG_SUSPEND>; > > + clock-names = "ref", "bus_early", "suspend"; > > + dr_mode = "host"; > > + usb-phy = <&usb3phy_utmi>, <&usb3phy_pipe>; > > + phy_type = "utmi_wide"; > > + snps,dis_enblslpm_quirk; > > + snps,dis-u2-freeclk-exists-quirk; > > + snps,dis_u2_susphy_quirk; > > + snps,dis_u3_susphy_quirk; > > + snps,dis-del-phy-power-chg-quirk; > > + snps,dis-tx-ipgap-linecheck-quirk; > > + snps,xhci-trb-ent-quirk; > > + status = "disabled"; > > + }; > > + }; > > + > > gic: interrupt-controller@ff811000 { > > compatible = "arm,gic-400"; > > #interrupt-cells = <3>; > > >
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index bbdb19a3e85d..9fea9203d114 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -853,6 +853,40 @@ u2phy_host: host-port { }; }; + usb3phy: usb3-phy@ff470000 { + compatible = "rockchip,rk3328-usb3phy"; + reg = <0x0 0xff460000 0x0 0x10000>; + clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; + clock-names = "usb3phy-otg", "usb3phy-pipe"; + resets = <&cru SRST_USB3PHY_U2>, + <&cru SRST_USB3PHY_U3>, + <&cru SRST_USB3PHY_PIPE>, + <&cru SRST_USB3OTG_UTMI>, + <&cru SRST_USB3PHY_OTG_P>, + <&cru SRST_USB3PHY_PIPE_P>; + reset-names = "usb3phy-u2-por", "usb3phy-u3-por", + "usb3phy-pipe-mac", "usb3phy-utmi-mac", + "usb3phy-utmi-apb", "usb3phy-pipe-apb"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb3phy_utmi: utmi@ff470000 { + compatible = "rockchip,rk3328-usb3phy-utmi"; + reg = <0x0 0xff470000 0x0 0x8000>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb3phy_pipe: pipe@ff478000 { + compatible = "rockchip,rk3328-usb3phy-pipe"; + reg = <0x0 0xff478000 0x0 0x8000>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + sdmmc: mmc@ff500000 { compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff500000 0x0 0x4000>; @@ -983,6 +1017,37 @@ usb_host0_ohci: usb@ff5d0000 { status = "disabled"; }; + usbdrd3: usb@ff600000 { + compatible = "rockchip,rk3328-dwc3"; + clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>, + <&cru SCLK_USB3OTG_SUSPEND>; + clock-names = "ref", "bus_early", "suspend"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3: dwc3@ff600000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff600000 0x0 0x100000>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_USB3OTG_REF>, <&cru ACLK_USB3OTG>, + <&cru SCLK_USB3OTG_SUSPEND>; + clock-names = "ref", "bus_early", "suspend"; + dr_mode = "host"; + usb-phy = <&usb3phy_utmi>, <&usb3phy_pipe>; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,xhci-trb-ent-quirk; + status = "disabled"; + }; + }; + gic: interrupt-controller@ff811000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;
Add the usb3 controller and usb3 phy nodes to the rk3328. Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 65 ++++++++++++++++++++++++ 1 file changed, 65 insertions(+)