| Message ID | 20201101100657.12087-10-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for DP-HDMI2.1 PCON | expand |
> -----Original Message----- > From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com> > Sent: Sunday, November 1, 2020 3:37 PM > To: intel-gfx@lists.freedesktop.org > Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>; > Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com; > Sharma, Swati2 <swati2.sharma@intel.com> > Subject: [PATCH v2 09/13] drm/i915: Check for FRL training before DP Link > training > > This patch calls functions to check FRL training requirements for an HDMI2.1 sink, > when connected through PCON. > The call is made before the DP link training. In case FRL is not required or failure > during FRL training, the TMDS mode is selected for the pcon. > > v2: moved check_frl_training() just after FEC READY, before starting DP link > training. Reviewed-by: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ > drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 09811be08cfe..3e76fb1117df 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3492,6 +3492,8 @@ static void tgl_ddi_pre_enable_dp(struct > intel_atomic_state *state, > */ > intel_dp_sink_set_fec_ready(intel_dp, crtc_state); > > + intel_dp_check_frl_training(intel_dp); > + > /* > * 7.i Follow DisplayPort specification training sequence (see notes for > * failure handling) > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 7feee2adf9b2..9047b620c0d0 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -4183,6 +4183,7 @@ static void intel_enable_dp(struct intel_atomic_state > *state, > > intel_dp_set_power(intel_dp, DP_SET_POWER_D0); > intel_dp_configure_protocol_converter(intel_dp); > + intel_dp_check_frl_training(intel_dp); > intel_dp_start_link_train(intel_dp, pipe_config); > intel_dp_stop_link_train(intel_dp, pipe_config); > > @@ -6104,6 +6105,7 @@ int intel_dp_retrain_link(struct intel_encoder > *encoder, > !intel_dp_mst_is_master_trans(crtc_state)) > continue; > > + intel_dp_check_frl_training(intel_dp); > intel_dp_start_link_train(intel_dp, crtc_state); > intel_dp_stop_link_train(intel_dp, crtc_state); > break; > -- > 2.17.1
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 09811be08cfe..3e76fb1117df 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3492,6 +3492,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, */ intel_dp_sink_set_fec_ready(intel_dp, crtc_state); + intel_dp_check_frl_training(intel_dp); + /* * 7.i Follow DisplayPort specification training sequence (see notes for * failure handling) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7feee2adf9b2..9047b620c0d0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4183,6 +4183,7 @@ static void intel_enable_dp(struct intel_atomic_state *state, intel_dp_set_power(intel_dp, DP_SET_POWER_D0); intel_dp_configure_protocol_converter(intel_dp); + intel_dp_check_frl_training(intel_dp); intel_dp_start_link_train(intel_dp, pipe_config); intel_dp_stop_link_train(intel_dp, pipe_config); @@ -6104,6 +6105,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, !intel_dp_mst_is_master_trans(crtc_state)) continue; + intel_dp_check_frl_training(intel_dp); intel_dp_start_link_train(intel_dp, crtc_state); intel_dp_stop_link_train(intel_dp, crtc_state); break;
This patch calls functions to check FRL training requirements for an HDMI2.1 sink, when connected through PCON. The call is made before the DP link training. In case FRL is not required or failure during FRL training, the TMDS mode is selected for the pcon. v2: moved check_frl_training() just after FEC READY, before starting DP link training. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ 2 files changed, 4 insertions(+)