[RFC,0/2] clk: sunxi-ng: a64: Remove CPUX mux switching

Message

Icenowy Zheng Nov. 9, 2020, 5:33 a.m. UTC

According to Ondrej Jirman, switching of the mux of CPUX clock is one of
the sources of timer jumps on A64 (and maybe this will also lead to
timer jump on H3).

This patchset tries to remove this mux by disabling the dividers in
PLL-CPUX. Both the lack of reparent when relocking and the prevention of
PLL-CPUX dividers are behaviors of the BSP kernel.

Icenowy Zheng (2):
  clk: sunxi-ng: a64: disable dividers in PLL-CPUX
  clk: sunxi-ng: a64: disable mux and pll notifiers for CPUX reclocking

 drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 93 ++++++++++++++++++++++-----
 1 file changed, 78 insertions(+), 15 deletions(-)

Comments

[e-mail] Nov. 20, 2020, 3:22 p.m. UTC | #1

On Mon, Nov 09, 2020 at 01:33:56PM +0800, Icenowy Zheng wrote:
> According to Ondrej Jirman, switching of the mux of CPUX clock is one of
> the sources of timer jumps on A64 (and maybe this will also lead to
> timer jump on H3).

Isn't the arch timer supposed to be clocked directly for the 24MHz
crystal? Either way, it would be great to have some explanations on why
this is the source of the timer jumps. It's like the third or fourth
time that claim is made, without completely fixing the issue so far

Maxime