| Message ID | 20201119080002.100342-1-tmaimon77@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | b2d91953b66c724eaf8d7f84f37c006d966f67ac |
| Headers | show |
| Series | [v1] ARM: dts: add Nuvoton NPCM730 device tree | expand |
On Thu, 19 Nov 2020 at 00:00, Tomer Maimon <tmaimon77@gmail.com> wrote: > > Add Nuvoton NPCM730 SoC device tree. > > The Nuvoton NPCN730 SoC is a part of the > Nuvoton NPCM7xx SoCs family. > > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Benjamin Fair <benjaminfair@google.com> > > --- > arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 ++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi > > diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi > new file mode 100644 > index 000000000000..86ec12ec2b50 > --- /dev/null > +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi > @@ -0,0 +1,44 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright (c) 2020 Nuvoton Technology > + > +#include "nuvoton-common-npcm7xx.dtsi" > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-parent = <&gic>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + enable-method = "nuvoton,npcm750-smp"; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk NPCM7XX_CLK_CPU>; > + clock-names = "clk_cpu"; > + reg = <0>; > + next-level-cache = <&l2>; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk NPCM7XX_CLK_CPU>; > + clock-names = "clk_cpu"; > + reg = <1>; > + next-level-cache = <&l2>; > + }; > + }; > + > + soc { > + timer@3fe600 { > + compatible = "arm,cortex-a9-twd-timer"; > + reg = <0x3fe600 0x20>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | > + IRQ_TYPE_LEVEL_HIGH)>; > + clocks = <&clk NPCM7XX_CLK_AHB>; > + }; > + }; > +}; > -- > 2.22.0 >
From: Arnd Bergmann <arnd@arndb.de> On Thu, 19 Nov 2020 10:00:02 +0200, Tomer Maimon wrote: > Add Nuvoton NPCM730 SoC device tree. > > The Nuvoton NPCN730 SoC is a part of the > Nuvoton NPCM7xx SoCs family. Applied to arm/dt, thanks! [1/1] ARM: dts: add Nuvoton NPCM730 device tree commit: b2d91953b66c724eaf8d7f84f37c006d966f67ac Arnd
diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi new file mode 100644 index 000000000000..86ec12ec2b50 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 Nuvoton Technology + +#include "nuvoton-common-npcm7xx.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + soc { + timer@3fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x3fe600 0x20>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&clk NPCM7XX_CLK_AHB>; + }; + }; +};
Add Nuvoton NPCM730 SoC device tree. The Nuvoton NPCN730 SoC is a part of the Nuvoton NPCM7xx SoCs family. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> --- arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 ++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi