@@ -361,25 +361,6 @@ static int ddr_perf_event_init(struct perf_event *event)
return 0;
}
-
-static void ddr_perf_event_update(struct perf_event *event)
-{
- struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
- struct hw_perf_event *hwc = &event->hw;
- u64 delta, prev_raw_count, new_raw_count;
- int counter = hwc->idx;
-
- do {
- prev_raw_count = local64_read(&hwc->prev_count);
- new_raw_count = ddr_perf_read_counter(pmu, counter);
- } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
- new_raw_count) != prev_raw_count);
-
- delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF;
-
- local64_add(delta, &event->count);
-}
-
static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
int counter, bool enable)
{
@@ -404,6 +385,56 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
}
}
+static bool ddr_perf_counter_overflow(struct ddr_pmu *pmu, int counter)
+{
+ int val;
+
+ val = readl_relaxed(pmu->base + counter * 4 + COUNTER_CNTL);
+
+ return val & CNTL_OVER;
+}
+
+static void ddr_perf_counter_clear(struct ddr_pmu *pmu, int counter)
+{
+ u8 reg = counter * 4 + COUNTER_CNTL;
+ int val;
+
+ val = readl_relaxed(pmu->base + reg);
+ val &= ~CNTL_CLEAR;
+ writel(val, pmu->base + reg);
+
+ val |= CNTL_CLEAR;
+ writel(val, pmu->base + reg);
+}
+
+static void ddr_perf_event_update(struct perf_event *event)
+{
+ struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+ u64 new_raw_count;
+ int counter = hwc->idx;
+ int ret;
+
+ new_raw_count = ddr_perf_read_counter(pmu, counter);
+ local64_add(new_raw_count, &event->count);
+
+ /*
+ * For legacy SoCs: event counter continue counting when overflow,
+ * no need to clear the counter.
+ * For new SoCs: event counter stop counting when overflow, need
+ * clear counter to let it count again.
+ */
+ if (counter != EVENT_CYCLES_COUNTER) {
+ ret = ddr_perf_counter_overflow(pmu, counter);
+ if (ret)
+ dev_warn_ratelimited(pmu->dev, "events lost due to counter overflow (config 0x%llx)\n",
+ event->attr.config);
+ }
+
+ /* clear counter every time for both cycle counter and event counter */
+ ddr_perf_counter_clear(pmu, counter);
+}
+
static void ddr_perf_event_start(struct perf_event *event, int flags)
{
struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
@@ -536,7 +567,7 @@ static irqreturn_t ddr_perf_irq_handler(int irq, void *p)
{
int i;
struct ddr_pmu *pmu = (struct ddr_pmu *) p;
- struct perf_event *event, *cycle_event = NULL;
+ struct perf_event *event;
/* all counter will stop if cycle counter disabled */
ddr_perf_counter_enable(pmu,
@@ -546,7 +577,9 @@ static irqreturn_t ddr_perf_irq_handler(int irq, void *p)
/*
* When the cycle counter overflows, all counters are stopped,
* and an IRQ is raised. If any other counter overflows, it
- * continues counting, and no IRQ is raised.
+ * continues counting, and no IRQ is raised. But for new SoCs,
+ * such as i.MX8MP, event counter would stop when overflow, so
+ * we need use cycle counter to stop overflow of event counter.
*
* Cycles occur at least 4 times as often as other events, so we
* can update all events on a cycle counter overflow and not
@@ -561,17 +594,12 @@ static irqreturn_t ddr_perf_irq_handler(int irq, void *p)
event = pmu->events[i];
ddr_perf_event_update(event);
-
- if (event->hw.idx == EVENT_CYCLES_COUNTER)
- cycle_event = event;
}
ddr_perf_counter_enable(pmu,
EVENT_CYCLES_ID,
EVENT_CYCLES_COUNTER,
true);
- if (cycle_event)
- ddr_perf_event_update(cycle_event);
return IRQ_HANDLED;
}
DDR Perf driver only supports free-running event counters(counter1/2/3) now, this patch adds support for stop event counters. Legacy SoCs: Cycle counter(counter0) is a special counter, only count cycles. When cycle counter overflow, it will lock all counters and generate an interrupt. In ddr_perf_irq_handler, disable cycle counter then all counters would stop at the same time, update all counters' count, then enable cycle counter that all counters count again. During this process, only clear cycle counter, no need to clear event counters since they are free-running counters. They would continue counting after overflow and do/while loop from ddr_perf_event_update can handle event counters overflow case. i.MX8MP: Almost all is the same as legacy SoCs, the only difference is that, event counters are not free-running any more. Like cycle counter, when event counters overflow, they would stop counting unless clear the counter, and no interrupt generate for event counters. So we should clear event counters that let them re-count when cycle counter overflow, which ensure event counters will not lose data. This patch adds stop event counters support which would be compatible to free-running event counters. We use the cycle counter to stop overflow of the event counters. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> --- ChangeLogs: V2->V3: * return val & CNTL_OVER ? true : false; -> return val & CNTL_OVER; * dev_warn() -> dev_warn_ratelimited() * treat cycle counter and event counter as the same way in update function. * add ddr_perf_counter_clear() V1->V2: * clear event counters in update function, instead of irq handler, so remove spinlock. --- drivers/perf/fsl_imx8_ddr_perf.c | 80 +++++++++++++++++++++----------- 1 file changed, 54 insertions(+), 26 deletions(-)