diff mbox series

[v2,14/18] arm: dts: owl-s500: Add SIRQ controller

Message ID db464acca3e30bfe5beaa3eb395c0664e2e7f3ad.1605823502.git.cristian.ciocaltea@gmail.com (mailing list archive)
State New, archived
Headers show
Series Add CMU/RMU/DMA/MMC/I2C support for Actions Semi S500 SoCs | expand

Commit Message

Cristian Ciocaltea Nov. 19, 2020, 11:56 p.m. UTC 
Add SIRQ controller node for Actions Semi S500 SoC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
 arch/arm/boot/dts/owl-s500.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Manivannan Sadhasivam Nov. 28, 2020, 7:35 a.m. UTC | #1 
On Fri, Nov 20, 2020 at 01:56:08AM +0200, Cristian Ciocaltea wrote:
> Add SIRQ controller node for Actions Semi S500 SoC.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
>  arch/arm/boot/dts/owl-s500.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
> index 55f8b8c2e149..cd635f222d26 100644
> --- a/arch/arm/boot/dts/owl-s500.dtsi
> +++ b/arch/arm/boot/dts/owl-s500.dtsi
> @@ -233,6 +233,16 @@ i2c3: i2c@b017c000 {
>  			status = "disabled";
>  		};
>  
> +		sirq: interrupt-controller@b01b0200 {
> +			compatible = "actions,s500-sirq";
> +			reg = <0xb01b0200 0x4>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
> +				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
> +				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
> +		};
> +
>  		timer: timer@b0168000 {
>  			compatible = "actions,s500-timer";
>  			reg = <0xb0168000 0x8000>;
> -- 
> 2.29.2
>
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 55f8b8c2e149..cd635f222d26 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -233,6 +233,16 @@  i2c3: i2c@b017c000 {
 			status = "disabled";
 		};
 
+		sirq: interrupt-controller@b01b0200 {
+			compatible = "actions,s500-sirq";
+			reg = <0xb01b0200 0x4>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
+				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
+				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
+		};
+
 		timer: timer@b0168000 {
 			compatible = "actions,s500-timer";
 			reg = <0xb0168000 0x8000>;