| Message ID | 20201202184415.1434484-1-f4bug@amsat.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | target/mips: Simplify MSA TCG logic | expand |
在 2020/12/3 上午2:44, Philippe Mathieu-Daudé 写道: > I converted MSA opcodes to decodetree. To keep the series > small I split it in 2, this is the non-decodetree specific > patches (so non-decodetree experts can review it ;) ). > > First we stop using env->insn_flags to check for MSAi > presence, then we restrict TCG functions to DisasContext*. Hi Philippe, For the whole series, Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> I'm just curious about how would you deal with so many condition flags with decodetree? Unlike other ISAs, MIPS have so many flavors, every ISA level (MIPS-III R2 R5 R6) has it's own instructions, and in my understanding decodetree file won't generate these switches. I was trying to do the same thing but soon find out we'll have around 20 decodertree for MIPS. Thanks. - Jiaxun > > Based-on: <20201130102228.2395100-1-f4bug@amsat.org> > "target/mips: Allow executing MSA instructions on Loongson-3A4000" > > Philippe Mathieu-Daudé (9): > target/mips: Introduce ase_msa_available() helper > target/mips: Simplify msa_reset() > target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA > target/mips: Simplify MSA TCG logic > target/mips: Remove now unused ASE_MSA definition > target/mips: Alias MSA vector registers on FPU scalar registers > target/mips: Extract msa_translate_init() from mips_tcg_init() > target/mips: Remove CPUMIPSState* argument from gen_msa*() methods > target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() > > target/mips/internal.h | 8 +- > target/mips/mips-defs.h | 1 - > target/mips/kvm.c | 12 +- > target/mips/translate.c | 206 ++++++++++++++++++------------- > target/mips/translate_init.c.inc | 12 +- > 5 files changed, 138 insertions(+), 101 deletions(-) >
在 2020/12/3 上午2:44, Philippe Mathieu-Daudé 写道: > I converted MSA opcodes to decodetree. To keep the series > small I split it in 2, this is the non-decodetree specific > patches (so non-decodetree experts can review it ;) ). > > First we stop using env->insn_flags to check for MSAi > presence, then we restrict TCG functions to DisasContext*. Hi Philippe, For the whole series, Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> I'm just curious about how would you deal with so many condition flags with decodetree? Unlike other ISAs, MIPS have so many flavors, every ISA level (MIPS-III R2 R5 R6) has it's own instructions, and in my understanding decodetree file won't generate these switches. I was trying to do the same thing but soon find out we'll have around 20 decodetree for MIPS. Thanks. - Jiaxun > > Based-on: <20201130102228.2395100-1-f4bug@amsat.org> > "target/mips: Allow executing MSA instructions on Loongson-3A4000" > > Philippe Mathieu-Daudé (9): > target/mips: Introduce ase_msa_available() helper > target/mips: Simplify msa_reset() > target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA > target/mips: Simplify MSA TCG logic > target/mips: Remove now unused ASE_MSA definition > target/mips: Alias MSA vector registers on FPU scalar registers > target/mips: Extract msa_translate_init() from mips_tcg_init() > target/mips: Remove CPUMIPSState* argument from gen_msa*() methods > target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() > > target/mips/internal.h | 8 +- > target/mips/mips-defs.h | 1 - > target/mips/kvm.c | 12 +- > target/mips/translate.c | 206 ++++++++++++++++++------------- > target/mips/translate_init.c.inc | 12 +- > 5 files changed, 138 insertions(+), 101 deletions(-) >