| Message ID | 20201204205804.25225-1-manasi.d.navare@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/display/dp: Compute the correct slice count for VDSC on DP | expand |
On 12/5/2020 2:28 AM, Manasi Navare wrote: > This patch fixes the slice count computation algorithm > for calculating the slice count based on Peak pixel rate > and the max slice width allowed on the DSC engines. > We need to ensure slice count > min slice count req > as per DP spec based on peak pixel rate and that it is > greater than min slice count based on the max slice width > advertised by DPCD. So use max of these two. > In the prev patch we were using min of these 2 causing it > to violate the max slice width limitation causing a blank > screen on 8K@60. > > Fixes: d9218c8f6cf4 ("drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC") > Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > Cc: Jani Nikula <jani.nikula@intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 2d4d5e95af84..cb5e42c3ecd5 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -615,7 +615,7 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, > return 0; > } > /* Also take into account max slice width */ > - min_slice_count = min_t(u8, min_slice_count, > + min_slice_count = max_t(u8, min_slice_count, > DIV_ROUND_UP(mode_hdisplay, > max_slice_width)); Change looks good to me. 'min_slice_count' is essentially the least no. of slices that would be sufficient. So max of the two values would be correct. Also tested with this change on an 8k panel, we are able get 8 DSC slices with this change, which is correct for 8k@60 resolution. Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> >
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 2d4d5e95af84..cb5e42c3ecd5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -615,7 +615,7 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, return 0; } /* Also take into account max slice width */ - min_slice_count = min_t(u8, min_slice_count, + min_slice_count = max_t(u8, min_slice_count, DIV_ROUND_UP(mode_hdisplay, max_slice_width));
This patch fixes the slice count computation algorithm for calculating the slice count based on Peak pixel rate and the max slice width allowed on the DSC engines. We need to ensure slice count > min slice count req as per DP spec based on peak pixel rate and that it is greater than min slice count based on the max slice width advertised by DPCD. So use max of these two. In the prev patch we were using min of these 2 causing it to violate the max slice width limitation causing a blank screen on 8K@60. Fixes: d9218c8f6cf4 ("drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC") Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)