| Message ID | 1607067224-15616-4-git-send-email-victor.liu@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | phy: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support | expand |
Hi Liu, Since we now gain optional properties validation would become even more useful. Could you look into converting to YAML before adding more values? Cheers, -- Guido On Fri, Dec 04, 2020 at 03:33:43PM +0800, Liu Ying wrote: > Add support for Mixel MIPI DPHY + LVDS PHY combo IP > as found on Freescale i.MX8qxp SoC. > > Cc: Guido Günther <agx@sigxcpu.org> > Cc: Kishon Vijay Abraham I <kishon@ti.com> > Cc: Vinod Koul <vkoul@kernel.org> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: NXP Linux Team <linux-imx@nxp.com> > Signed-off-by: Liu Ying <victor.liu@nxp.com> > --- > Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt > index 9b23407..0afce99 100644 > --- a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt > +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt > @@ -4,9 +4,13 @@ The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the > MIPI-DSI IP from Northwest Logic). It represents the physical layer for the > electrical signals for DSI. > > +The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work > +in either MIPI-DSI PHY mode or LVDS PHY mode. > + > Required properties: > -- compatible: Must be: > +- compatible: Should be one of: > - "fsl,imx8mq-mipi-dphy" > + - "fsl,imx8qxp-mipi-dphy" > - clocks: Must contain an entry for each entry in clock-names. > - clock-names: Must contain the following entries: > - "phy_ref": phandle and specifier referring to the DPHY ref clock > @@ -14,6 +18,8 @@ Required properties: > - #phy-cells: number of cells in PHY, as defined in > Documentation/devicetree/bindings/phy/phy-bindings.txt > this must be <0> > +- fsl,syscon: Phandle to a system controller, as required by the PHY > + in i.MX8qxp SoC. > > Optional properties: > - power-domains: phandle to power domain > -- > 2.7.4 >
On Tue, 2020-12-08 at 10:07 +0100, Guido Günther wrote: > Hi Liu, > Since we now gain optional properties validation would become even more > useful. Could you look into converting to YAML before adding more > values? Yes, a YAML one would be good. I'll try to do the conversion and then add the binding support for the i.MX8qxp Mixel combo PHY in it. Liu Ying > Cheers, > -- Guido > > On Fri, Dec 04, 2020 at 03:33:43PM +0800, Liu Ying wrote: > > Add support for Mixel MIPI DPHY + LVDS PHY combo IP > > as found on Freescale i.MX8qxp SoC. > > > > Cc: Guido Günther <agx@sigxcpu.org> > > Cc: Kishon Vijay Abraham I <kishon@ti.com> > > Cc: Vinod Koul <vkoul@kernel.org> > > Cc: Rob Herring <robh+dt@kernel.org> > > Cc: NXP Linux Team <linux-imx@nxp.com> > > Signed-off-by: Liu Ying <victor.liu@nxp.com> > > --- > > Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt | 8 +++++++- > > 1 file changed, 7 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt > > index 9b23407..0afce99 100644 > > --- a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt > > +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt > > @@ -4,9 +4,13 @@ The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the > > MIPI-DSI IP from Northwest Logic). It represents the physical layer for the > > electrical signals for DSI. > > > > +The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work > > +in either MIPI-DSI PHY mode or LVDS PHY mode. > > + > > Required properties: > > -- compatible: Must be: > > +- compatible: Should be one of: > > - "fsl,imx8mq-mipi-dphy" > > + - "fsl,imx8qxp-mipi-dphy" > > - clocks: Must contain an entry for each entry in clock-names. > > - clock-names: Must contain the following entries: > > - "phy_ref": phandle and specifier referring to the DPHY ref clock > > @@ -14,6 +18,8 @@ Required properties: > > - #phy-cells: number of cells in PHY, as defined in > > Documentation/devicetree/bindings/phy/phy-bindings.txt > > this must be <0> > > +- fsl,syscon: Phandle to a system controller, as required by the PHY > > + in i.MX8qxp SoC. > > > > Optional properties: > > - power-domains: phandle to power domain > > -- > > 2.7.4 > >
diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt index 9b23407..0afce99 100644 --- a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt @@ -4,9 +4,13 @@ The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the MIPI-DSI IP from Northwest Logic). It represents the physical layer for the electrical signals for DSI. +The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work +in either MIPI-DSI PHY mode or LVDS PHY mode. + Required properties: -- compatible: Must be: +- compatible: Should be one of: - "fsl,imx8mq-mipi-dphy" + - "fsl,imx8qxp-mipi-dphy" - clocks: Must contain an entry for each entry in clock-names. - clock-names: Must contain the following entries: - "phy_ref": phandle and specifier referring to the DPHY ref clock @@ -14,6 +18,8 @@ Required properties: - #phy-cells: number of cells in PHY, as defined in Documentation/devicetree/bindings/phy/phy-bindings.txt this must be <0> +- fsl,syscon: Phandle to a system controller, as required by the PHY + in i.MX8qxp SoC. Optional properties: - power-domains: phandle to power domain
Add support for Mixel MIPI DPHY + LVDS PHY combo IP as found on Freescale i.MX8qxp SoC. Cc: Guido Günther <agx@sigxcpu.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: NXP Linux Team <linux-imx@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> --- Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)