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[1/2] dt-bindings: qcom_nandc: Add SDX55 QPIC NAND documentation

Message ID 20201126085705.48399-2-manivannan.sadhasivam@linaro.org (mailing list archive)
State New, archived
Headers show
Series Add NAND support for SDX55 | expand

Commit Message

Manivannan Sadhasivam Nov. 26, 2020, 8:57 a.m. UTC 
Qualcomm SDX55 uses QPIC NAND controller version 2.0.0 with BAM DMA
Engine.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 2 ++
 1 file changed, 2 insertions(+)

Comments

Rob Herring Dec. 8, 2020, 4:08 p.m. UTC | #1 
On Thu, 26 Nov 2020 14:27:04 +0530, Manivannan Sadhasivam wrote:
> Qualcomm SDX55 uses QPIC NAND controller version 2.0.0 with BAM DMA
> Engine.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>  Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index 5c2fba4b30fe..a971db361678 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -8,6 +8,8 @@  Required properties:
                             IPQ4019 SoC and it uses BAM DMA
     * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
                             IPQ8074 SoC and it uses BAM DMA
+    * "qcom,sdx55-nand"   - for QPIC NAND controller v2.0.0 being used in
+                            SDX55 SoC and it uses BAM DMA
 
 - reg:			MMIO address range
 - clocks:		must contain core clock and always on clock