| Message ID | 956cf336ffce24f0cabfc7a98ae855bc71d5f028.1607524536.git.bertrand.marquis@arm.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | xen/arm: Emulate ID registers | expand |
On Wed, 9 Dec 2020, Bertrand Marquis wrote: > Activate TID3 bit in HSR register when starting a guest. > This will trap all coprecessor ID registers so that we can give to guest > values corresponding to what they can actually use and mask some > features to guests even though they would be supported by the underlying > hardware (like SVE or MPAM). > > Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> > --- > Changes in V2: Rebase > Changes in V3: Rebase > > --- > xen/arch/arm/traps.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c > index 28d9d64558..c1a9ad6056 100644 > --- a/xen/arch/arm/traps.c > +++ b/xen/arch/arm/traps.c > @@ -98,7 +98,7 @@ register_t get_default_hcr_flags(void) > { > return (HCR_PTW|HCR_BSU_INNER|HCR_AMO|HCR_IMO|HCR_FMO|HCR_VM| > (vwfi != NATIVE ? (HCR_TWI|HCR_TWE) : 0) | > - HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB|HCR_TSW); > + HCR_TID3|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB|HCR_TSW); > } > > static enum { > -- > 2.17.1 >
Hi Bertrand, On 09/12/2020 16:31, Bertrand Marquis wrote: > Activate TID3 bit in HSR register when starting a guest. s/HSR/HCR/ > This will trap all coprecessor ID registers so that we can give to guest > values corresponding to what they can actually use and mask some > features to guests even though they would be supported by the underlying > hardware (like SVE or MPAM). So this will make sure the guest will not be able to identify the feature. Did you check that the features are effectively not accessible by the guest? IOW it should trap. Cheers,
Hi Julien, > On 9 Dec 2020, at 23:17, Julien Grall <julien@xen.org> wrote: > > Hi Bertrand, > > On 09/12/2020 16:31, Bertrand Marquis wrote: >> Activate TID3 bit in HSR register when starting a guest. > > s/HSR/HCR/ > Right, I did it a lot thanks for the review. I will fix that in V4. >> This will trap all coprecessor ID registers so that we can give to guest >> values corresponding to what they can actually use and mask some >> features to guests even though they would be supported by the underlying >> hardware (like SVE or MPAM). > > So this will make sure the guest will not be able to identify the feature. Did you check that the features are effectively not accessible by the guest? IOW it should trap. For SVE yes I checked and with the serie a Linux kernel with SVE support activated on a target with SVE is now working (was crashing before). For MPAM, I have no target available with MPAM support so I could not test that but your recent XSA patch did turn the access to the guest off. With my SVE test, I could confirm that access are trapped and properly emulated. Cheers Bertrand > > Cheers, > > -- > Julien Grall >
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 28d9d64558..c1a9ad6056 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -98,7 +98,7 @@ register_t get_default_hcr_flags(void) { return (HCR_PTW|HCR_BSU_INNER|HCR_AMO|HCR_IMO|HCR_FMO|HCR_VM| (vwfi != NATIVE ? (HCR_TWI|HCR_TWE) : 0) | - HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB|HCR_TSW); + HCR_TID3|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB|HCR_TSW); } static enum {
Activate TID3 bit in HSR register when starting a guest. This will trap all coprecessor ID registers so that we can give to guest values corresponding to what they can actually use and mask some features to guests even though they would be supported by the underlying hardware (like SVE or MPAM). Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com> --- Changes in V2: Rebase Changes in V3: Rebase --- xen/arch/arm/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)