| Message ID | 20201210124917.24185-1-kishon@ti.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | PCI: J7: J7200/J721E PCIe bindings | expand |
On Thu, 10 Dec 2020 18:19:13 +0530, Kishon Vijay Abraham I wrote: > Patch series adds PCIe binding for J7200 and and fixes > "ti,syscon-pcie-ctrl" applicable to both J721E and J7200. > > All the four patches here have got Acks from Rob Herring. > > Ack for "dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take > argument" > lore.kernel.org/r/CAL_JsqJQju8TUZA-wu=WA-5XH4H9s2ifO8Hf4TnT5epa=Gg1ng@mail.gmail.com > > [...] Applied to pci/cadence, thanks! [1/4] dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument https://git.kernel.org/lpieralisi/pci/c/b6c81be912 [2/4] dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC https://git.kernel.org/lpieralisi/pci/c/3f1f870c01 [3/4] dt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC https://git.kernel.org/lpieralisi/pci/c/17c5b458a9 [4/4] PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg https://git.kernel.org/lpieralisi/pci/c/7aa256234c Thanks, Lorenzo
Patch series adds PCIe binding for J7200 and and fixes "ti,syscon-pcie-ctrl" applicable to both J721E and J7200. All the four patches here have got Acks from Rob Herring. Ack for "dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument" lore.kernel.org/r/CAL_JsqJQju8TUZA-wu=WA-5XH4H9s2ifO8Hf4TnT5epa=Gg1ng@mail.gmail.com Ack for "dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC" lore.kernel.org/r/20201105165604.GA1474027@bogus Ack for "dt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC" http://lore.kernel.org/r/20201105165627.GA1474647@bogus Ack for "PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg" http://lore.kernel.org/r/CAL_JsqKQwx2qKJb5eAsutdHH5DevC+XH33yXrCBWE+OCrrQFYg@mail.gmail.com Kishon Vijay Abraham I (4): dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC dt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg .../bindings/pci/ti,j721e-pci-ep.yaml | 21 ++++++++++---- .../bindings/pci/ti,j721e-pci-host.yaml | 27 +++++++++++++----- drivers/pci/controller/cadence/pci-j721e.c | 28 +++++++++++++------ 3 files changed, 54 insertions(+), 22 deletions(-)