| Message ID | 20201214113041.2789043-1-idosch@idosch.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | mlxsw: Introduce initial XM router support | expand |
Hello: This series was applied to netdev/net-next.git (refs/heads/master): On Mon, 14 Dec 2020 13:30:26 +0200 you wrote: > From: Ido Schimmel <idosch@nvidia.com> > > This patch set implements initial eXtended Mezzanine (XM) router > support. > > The XM is an external device connected to the Spectrum-{2,3} ASICs using > dedicated Ethernet ports. Its purpose is to increase the number of > routes that can be offloaded to hardware. This is achieved by having the > ASIC act as a cache that refers cache misses to the XM where the FIB is > stored and LPM lookup is performed. > > [...] Here is the summary with links: - [net-next,v2,01/15] mlxsw: reg: Add XM Direct Register https://git.kernel.org/netdev/net-next/c/be6ba3b61e20 - [net-next,v2,02/15] mlxsw: reg: Add Router XLT Enable Register https://git.kernel.org/netdev/net-next/c/6100fbf13d2f - [net-next,v2,03/15] mlxsw: spectrum_router: Introduce XM implementation of router low-level ops https://git.kernel.org/netdev/net-next/c/ff462103ca4d - [net-next,v2,04/15] mlxsw: pci: Obtain info about ports used by eXtended mezanine https://git.kernel.org/netdev/net-next/c/2ea3f4c7fa7c - [net-next,v2,05/15] mlxsw: Ignore ports that are connected to eXtended mezanine https://git.kernel.org/netdev/net-next/c/50779c332556 - [net-next,v2,06/15] mlxsw: reg: Add Router XLT M select Register https://git.kernel.org/netdev/net-next/c/087489dc2748 - [net-next,v2,07/15] mlxsw: reg: Add XM Lookup Table Query Register https://git.kernel.org/netdev/net-next/c/ec54677e55bb - [net-next,v2,08/15] mlxsw: spectrum_router: Introduce per-ASIC XM initialization https://git.kernel.org/netdev/net-next/c/e0bc244dcf58 - [net-next,v2,09/15] mlxsw: reg: Add XM Router M Table Register https://git.kernel.org/netdev/net-next/c/e35e80464896 - [net-next,v2,10/15] mlxsw: spectrum_router_xm: Implement L-value tracking for M-index https://git.kernel.org/netdev/net-next/c/54ff9dbbb96f - [net-next,v2,11/15] mlxsw: reg: Add Router LPM Cache ML Delete Register https://git.kernel.org/netdev/net-next/c/edb47f3d2368 - [net-next,v2,12/15] mlxsw: reg: Add Router LPM Cache Enable Register https://git.kernel.org/netdev/net-next/c/069254662b65 - [net-next,v2,13/15] mlxsw: spectrum_router_xm: Introduce basic XM cache flushing https://git.kernel.org/netdev/net-next/c/2dfad87a24de - [net-next,v2,14/15] mlxsw: spectrum: Set KVH XLT cache mode for Spectrum2/3 https://git.kernel.org/netdev/net-next/c/dffd566136d7 - [net-next,v2,15/15] mlxsw: spectrum_router: Use eXtended mezzanine to offload IPv4 router https://git.kernel.org/netdev/net-next/c/88a31b18b6df You are awesome, thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html
From: Ido Schimmel <idosch@nvidia.com> This patch set implements initial eXtended Mezzanine (XM) router support. The XM is an external device connected to the Spectrum-{2,3} ASICs using dedicated Ethernet ports. Its purpose is to increase the number of routes that can be offloaded to hardware. This is achieved by having the ASIC act as a cache that refers cache misses to the XM where the FIB is stored and LPM lookup is performed. Future patch sets will add more sophisticated cache flushing and selftests that utilize cache counters on the ASIC, which we plan to expose via devlink-metric [1]. Patch set overview: Patches #1-#2 add registers to insert/remove routes to/from the XM and to enable/disable it. Patch #3 utilizes these registers in order to implement XM-specific router low-level operations. Patches #4-#5 query from firmware the availability of the XM and the local ports that are used to connect the ASIC to the XM, so that netdevs will not be created for them. Patches #6-#8 initialize the XM by configuring its cache parameters. Patch #9-#10 implement cache management, so that LPM lookup will be correctly cached in the ASIC. Patches #11-#13 implement cache flushing, so that routes insertions/removals to/from the XM will flush the affected entries in the cache. Patch #14 configures the ASIC to allocate half of its memory for the cache, so that room will be left for other entries (e.g., FDBs, neighbours). Patch #15 starts using the XM for IPv4 route offload, when available. v2: * Patch #13: Fix GENMASK() high bit to build correctly on 32 bits (Jakub) [1] https://lore.kernel.org/netdev/20200817125059.193242-1-idosch@idosch.org/ Jiri Pirko (15): mlxsw: reg: Add XM Direct Register mlxsw: reg: Add Router XLT Enable Register mlxsw: spectrum_router: Introduce XM implementation of router low-level ops mlxsw: pci: Obtain info about ports used by eXtended mezanine mlxsw: Ignore ports that are connected to eXtended mezanine mlxsw: reg: Add Router XLT M select Register mlxsw: reg: Add XM Lookup Table Query Register mlxsw: spectrum_router: Introduce per-ASIC XM initialization mlxsw: reg: Add XM Router M Table Register mlxsw: spectrum_router_xm: Implement L-value tracking for M-index mlxsw: reg: Add Router LPM Cache ML Delete Register mlxsw: reg: Add Router LPM Cache Enable Register mlxsw: spectrum_router_xm: Introduce basic XM cache flushing mlxsw: spectrum: Set KVH XLT cache mode for Spectrum2/3 mlxsw: spectrum_router: Use eXtended mezzanine to offload IPv4 router drivers/net/ethernet/mellanox/mlxsw/Makefile | 1 + drivers/net/ethernet/mellanox/mlxsw/cmd.h | 30 + drivers/net/ethernet/mellanox/mlxsw/core.c | 12 + drivers/net/ethernet/mellanox/mlxsw/core.h | 12 +- drivers/net/ethernet/mellanox/mlxsw/minimal.c | 3 +- drivers/net/ethernet/mellanox/mlxsw/pci.c | 33 +- drivers/net/ethernet/mellanox/mlxsw/reg.h | 585 ++++++++++++- .../net/ethernet/mellanox/mlxsw/spectrum.c | 5 + .../ethernet/mellanox/mlxsw/spectrum_router.c | 23 +- .../ethernet/mellanox/mlxsw/spectrum_router.h | 10 + .../mellanox/mlxsw/spectrum_router_xm.c | 812 ++++++++++++++++++ 11 files changed, 1518 insertions(+), 8 deletions(-) create mode 100644 drivers/net/ethernet/mellanox/mlxsw/spectrum_router_xm.c