diff mbox series

[v2,3/5] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h

Message ID 20201215114828.18076-4-leif@nuviainc.com (mailing list archive)
State New, archived
Headers show
Series target/arm: various changes to cpu.h | expand

Commit Message

Leif Lindholm Dec. 15, 2020, 11:48 a.m. UTC 
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
---
 target/arm/cpu.h | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

Comments

Laurent Desnogues Dec. 15, 2020, 12:23 p.m. UTC | #1 
Hello,

On Tue, Dec 15, 2020 at 12:51 PM Leif Lindholm <leif@nuviainc.com> wrote:
>
> Signed-off-by: Leif Lindholm <leif@nuviainc.com>
> ---
>  target/arm/cpu.h | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index fadd1a47df..90ba707b64 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1736,6 +1736,30 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
>  /*
>   * System register ID fields.
>   */
> +FIELD(CLIDR_EL1, CTYPE1, 0, 3)
> +FIELD(CLIDR_EL1, CTYPE2, 3, 3)
> +FIELD(CLIDR_EL1, CTYPE3, 6, 3)
> +FIELD(CLIDR_EL1, CTYPE4, 9, 3)
> +FIELD(CLIDR_EL1, CTYPE5, 12, 3)
> +FIELD(CLIDR_EL1, CTYPE6, 15, 3)
> +FIELD(CLIDR_EL1, CTYPE7, 18, 3)
> +FIELD(CLIDR_EL1, LOUIS, 21, 3)
> +FIELD(CLIDR_EL1, LOC, 24, 3)
> +FIELD(CLIDR_EL1, LOUU, 27, 3)
> +FIELD(CLIDR_EL1, ICB, 30, 3)
> +
> +FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 21)
> +FIELD(CCSIDR_EL1, NUMSETS, 32, 24)

The positions and sizes of the ASSOCIATIVITY and NUMSETS CCSIDR fields
depend on whether the ARMv8.3-CCIDX extension is implemented or not.
If we really want to define the fields this way, we perhaps should
define two sets.  Or at the very least, add a comment stating this
definition is for ARMv8.3-CCIDX.

> +FIELD(CTR_EL0,  IMINLINE, 0, 4)
> +FIELD(CTR_EL0,  L1IP, 14, 2)
> +FIELD(CTR_EL0,  DMINLINE, 16, 4)
> +FIELD(CTR_EL0,  ERG, 20, 4)
> +FIELD(CTR_EL0,  CWG, 24, 4)
> +FIELD(CTR_EL0,  IDC, 28, 1)
> +FIELD(CTR_EL0,  DIC, 29, 1)

There's a missing field:  TminLine which starts at bit 32.  If
implemented, that would require to make ctr a 64-bit integer.

Thanks,

Laurent

> +
>  FIELD(MIDR_EL1, REVISION, 0, 4)
>  FIELD(MIDR_EL1, PARTNUM, 4, 12)
>  FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
> --
> 2.20.1
>
>
Leif Lindholm Dec. 15, 2020, 4:49 p.m. UTC | #2 
On Tue, Dec 15, 2020 at 13:23:58 +0100, Laurent Desnogues wrote:
> Hello,
> 
> On Tue, Dec 15, 2020 at 12:51 PM Leif Lindholm <leif@nuviainc.com> wrote:
> >
> > Signed-off-by: Leif Lindholm <leif@nuviainc.com>
> > ---
> >  target/arm/cpu.h | 24 ++++++++++++++++++++++++
> >  1 file changed, 24 insertions(+)
> >
> > diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> > index fadd1a47df..90ba707b64 100644
> > --- a/target/arm/cpu.h
> > +++ b/target/arm/cpu.h
> > @@ -1736,6 +1736,30 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
> >  /*
> >   * System register ID fields.
> >   */
> > +FIELD(CLIDR_EL1, CTYPE1, 0, 3)
> > +FIELD(CLIDR_EL1, CTYPE2, 3, 3)
> > +FIELD(CLIDR_EL1, CTYPE3, 6, 3)
> > +FIELD(CLIDR_EL1, CTYPE4, 9, 3)
> > +FIELD(CLIDR_EL1, CTYPE5, 12, 3)
> > +FIELD(CLIDR_EL1, CTYPE6, 15, 3)
> > +FIELD(CLIDR_EL1, CTYPE7, 18, 3)
> > +FIELD(CLIDR_EL1, LOUIS, 21, 3)
> > +FIELD(CLIDR_EL1, LOC, 24, 3)
> > +FIELD(CLIDR_EL1, LOUU, 27, 3)
> > +FIELD(CLIDR_EL1, ICB, 30, 3)
> > +
> > +FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 21)
> > +FIELD(CCSIDR_EL1, NUMSETS, 32, 24)
> 
> The positions and sizes of the ASSOCIATIVITY and NUMSETS CCSIDR fields
> depend on whether the ARMv8.3-CCIDX extension is implemented or not.
> If we really want to define the fields this way, we perhaps should
> define two sets.  Or at the very least, add a comment stating this
> definition is for ARMv8.3-CCIDX.

Urgh, sorry for this.
I added the fields only to make the CPU definition more readable, so I
think we don't need to worry about runtime handling of this?
But I don't think it makes sense to add only the one form.
Should I use CCIDX_CCSIDR_EL1 for these ones and add

/* When FEAT_CCIDX is not implemented */
FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
FIELD(CCSIDR_EL1, NUMSETS, 13, 15)

with a comment that
/* When FEAT_CCIDX is implemented */
for the former set
?

> > +FIELD(CTR_EL0,  IMINLINE, 0, 4)
> > +FIELD(CTR_EL0,  L1IP, 14, 2)
> > +FIELD(CTR_EL0,  DMINLINE, 16, 4)
> > +FIELD(CTR_EL0,  ERG, 20, 4)
> > +FIELD(CTR_EL0,  CWG, 24, 4)
> > +FIELD(CTR_EL0,  IDC, 28, 1)
> > +FIELD(CTR_EL0,  DIC, 29, 1)
> 
> There's a missing field:  TminLine which starts at bit 32.

Ack, oops.

> If
> implemented, that would require to make ctr a 64-bit integer.

As far as I can tell, this will be safe with existing code - should I
fold in a patch extending the register?

Regards,

Leif

> Thanks,
> 
> Laurent
> 
> > +
> >  FIELD(MIDR_EL1, REVISION, 0, 4)
> >  FIELD(MIDR_EL1, PARTNUM, 4, 12)
> >  FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
> > --
> > 2.20.1
> >
> >
Laurent Desnogues Dec. 17, 2020, 10:02 a.m. UTC | #3 
Hi Leif,

On Tue, Dec 15, 2020 at 5:49 PM Leif Lindholm <leif@nuviainc.com> wrote:
>
> On Tue, Dec 15, 2020 at 13:23:58 +0100, Laurent Desnogues wrote:
> > Hello,
> >
> > On Tue, Dec 15, 2020 at 12:51 PM Leif Lindholm <leif@nuviainc.com> wrote:
> > >
> > > Signed-off-by: Leif Lindholm <leif@nuviainc.com>
> > > ---
> > >  target/arm/cpu.h | 24 ++++++++++++++++++++++++
> > >  1 file changed, 24 insertions(+)
> > >
> > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> > > index fadd1a47df..90ba707b64 100644
> > > --- a/target/arm/cpu.h
> > > +++ b/target/arm/cpu.h
> > > @@ -1736,6 +1736,30 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
> > >  /*
> > >   * System register ID fields.
> > >   */
> > > +FIELD(CLIDR_EL1, CTYPE1, 0, 3)
> > > +FIELD(CLIDR_EL1, CTYPE2, 3, 3)
> > > +FIELD(CLIDR_EL1, CTYPE3, 6, 3)
> > > +FIELD(CLIDR_EL1, CTYPE4, 9, 3)
> > > +FIELD(CLIDR_EL1, CTYPE5, 12, 3)
> > > +FIELD(CLIDR_EL1, CTYPE6, 15, 3)
> > > +FIELD(CLIDR_EL1, CTYPE7, 18, 3)
> > > +FIELD(CLIDR_EL1, LOUIS, 21, 3)
> > > +FIELD(CLIDR_EL1, LOC, 24, 3)
> > > +FIELD(CLIDR_EL1, LOUU, 27, 3)
> > > +FIELD(CLIDR_EL1, ICB, 30, 3)
> > > +
> > > +FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > > +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 21)
> > > +FIELD(CCSIDR_EL1, NUMSETS, 32, 24)
> >
> > The positions and sizes of the ASSOCIATIVITY and NUMSETS CCSIDR fields
> > depend on whether the ARMv8.3-CCIDX extension is implemented or not.
> > If we really want to define the fields this way, we perhaps should
> > define two sets.  Or at the very least, add a comment stating this
> > definition is for ARMv8.3-CCIDX.
>
> Urgh, sorry for this.
> I added the fields only to make the CPU definition more readable, so I
> think we don't need to worry about runtime handling of this?
> But I don't think it makes sense to add only the one form.
> Should I use CCIDX_CCSIDR_EL1 for these ones and add
>
> /* When FEAT_CCIDX is not implemented */
> FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
> FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
>
> with a comment that
> /* When FEAT_CCIDX is implemented */
> for the former set
> ?

Having both would be handy, but you need to have different names for
the fields.  For setting fields up in cpu{64}.c that'd be acceptable
as you know if the CPU you define has ARMv8.3-CCIDX. In the rest of
the code the use would be more complicated as you'd have to check for
ARMv8.3-CCIDX before accessing fields.  But the use of those fields
outside of cpu{64}.c would likely be extremely limited so I don't
think that's an issue.

> > > +FIELD(CTR_EL0,  IMINLINE, 0, 4)
> > > +FIELD(CTR_EL0,  L1IP, 14, 2)
> > > +FIELD(CTR_EL0,  DMINLINE, 16, 4)
> > > +FIELD(CTR_EL0,  ERG, 20, 4)
> > > +FIELD(CTR_EL0,  CWG, 24, 4)
> > > +FIELD(CTR_EL0,  IDC, 28, 1)
> > > +FIELD(CTR_EL0,  DIC, 29, 1)
> >
> > There's a missing field:  TminLine which starts at bit 32.
>
> Ack, oops.
>
> > If
> > implemented, that would require to make ctr a 64-bit integer.
>
> As far as I can tell, this will be safe with existing code - should I
> fold in a patch extending the register?

IMHO it'd be better to extend ctr to 64-bit.  But I'm not sure of the
implications in the rest of the code.

Thanks,

Laurent

> Regards,
>
> Leif
>
> > Thanks,
> >
> > Laurent
> >
> > > +
> > >  FIELD(MIDR_EL1, REVISION, 0, 4)
> > >  FIELD(MIDR_EL1, PARTNUM, 4, 12)
> > >  FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
> > > --
> > > 2.20.1
> > >
> > >
Leif Lindholm Dec. 17, 2020, 12:10 p.m. UTC | #4 
Hi Laurent,

On Thu, Dec 17, 2020 at 11:02:23 +0100, Laurent Desnogues wrote:
> Hi Leif,
> 
> On Tue, Dec 15, 2020 at 5:49 PM Leif Lindholm <leif@nuviainc.com> wrote:
> >
> > On Tue, Dec 15, 2020 at 13:23:58 +0100, Laurent Desnogues wrote:
> > > Hello,
> > >
> > > On Tue, Dec 15, 2020 at 12:51 PM Leif Lindholm <leif@nuviainc.com> wrote:
> > > >
> > > > Signed-off-by: Leif Lindholm <leif@nuviainc.com>
> > > > ---
> > > >  target/arm/cpu.h | 24 ++++++++++++++++++++++++
> > > >  1 file changed, 24 insertions(+)
> > > >
> > > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> > > > index fadd1a47df..90ba707b64 100644
> > > > --- a/target/arm/cpu.h
> > > > +++ b/target/arm/cpu.h
> > > > @@ -1736,6 +1736,30 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
> > > >  /*
> > > >   * System register ID fields.
> > > >   */
> > > > +FIELD(CLIDR_EL1, CTYPE1, 0, 3)
> > > > +FIELD(CLIDR_EL1, CTYPE2, 3, 3)
> > > > +FIELD(CLIDR_EL1, CTYPE3, 6, 3)
> > > > +FIELD(CLIDR_EL1, CTYPE4, 9, 3)
> > > > +FIELD(CLIDR_EL1, CTYPE5, 12, 3)
> > > > +FIELD(CLIDR_EL1, CTYPE6, 15, 3)
> > > > +FIELD(CLIDR_EL1, CTYPE7, 18, 3)
> > > > +FIELD(CLIDR_EL1, LOUIS, 21, 3)
> > > > +FIELD(CLIDR_EL1, LOC, 24, 3)
> > > > +FIELD(CLIDR_EL1, LOUU, 27, 3)
> > > > +FIELD(CLIDR_EL1, ICB, 30, 3)
> > > > +
> > > > +FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > > > +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 21)
> > > > +FIELD(CCSIDR_EL1, NUMSETS, 32, 24)
> > >
> > > The positions and sizes of the ASSOCIATIVITY and NUMSETS CCSIDR fields
> > > depend on whether the ARMv8.3-CCIDX extension is implemented or not.
> > > If we really want to define the fields this way, we perhaps should
> > > define two sets.  Or at the very least, add a comment stating this
> > > definition is for ARMv8.3-CCIDX.
> >
> > Urgh, sorry for this.
> > I added the fields only to make the CPU definition more readable, so I
> > think we don't need to worry about runtime handling of this?
> > But I don't think it makes sense to add only the one form.
> > Should I use CCIDX_CCSIDR_EL1 for these ones and add
> >
> > /* When FEAT_CCIDX is not implemented */
> > FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
> > FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
> >
> > with a comment that
> > /* When FEAT_CCIDX is implemented */
> > for the former set
> > ?
> 
> Having both would be handy, but you need to have different names for
> the fields.

Different names for the same field?
I.e.
FIELD(CCIDX_CCSIDR_EL1, LINESIZE, 0, 3)
would need a different name for LINESIZE than
FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
?

> For setting fields up in cpu{64}.c that'd be acceptable
> as you know if the CPU you define has ARMv8.3-CCIDX. In the rest of
> the code the use would be more complicated as you'd have to check for
> ARMv8.3-CCIDX before accessing fields.  But the use of those fields
> outside of cpu{64}.c would likely be extremely limited so I don't
> think that's an issue.

Yeah, QEMU itself currently doesn't look into the fields at all.

> > > > +FIELD(CTR_EL0,  IMINLINE, 0, 4)
> > > > +FIELD(CTR_EL0,  L1IP, 14, 2)
> > > > +FIELD(CTR_EL0,  DMINLINE, 16, 4)
> > > > +FIELD(CTR_EL0,  ERG, 20, 4)
> > > > +FIELD(CTR_EL0,  CWG, 24, 4)
> > > > +FIELD(CTR_EL0,  IDC, 28, 1)
> > > > +FIELD(CTR_EL0,  DIC, 29, 1)
> > >
> > > There's a missing field:  TminLine which starts at bit 32.
> >
> > Ack, oops.
> >
> > > If
> > > implemented, that would require to make ctr a 64-bit integer.
> >
> > As far as I can tell, this will be safe with existing code - should I
> > fold in a patch extending the register?
> 
> IMHO it'd be better to extend ctr to 64-bit.  But I'm not sure of the
> implications in the rest of the code.

Sorry, I was ambivalent in my message: I meant that (at a glance it
looked like) existing code should be fine with extending it to
64-bit. So I'll do that.

Best Regards,

Leif

> 
> Thanks,
> 
> Laurent
> 
> > Regards,
> >
> > Leif
> >
> > > Thanks,
> > >
> > > Laurent
> > >
> > > > +
> > > >  FIELD(MIDR_EL1, REVISION, 0, 4)
> > > >  FIELD(MIDR_EL1, PARTNUM, 4, 12)
> > > >  FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
> > > > --
> > > > 2.20.1
> > > >
> > > >
Laurent Desnogues Dec. 17, 2020, 12:18 p.m. UTC | #5 
On Thu, Dec 17, 2020 at 1:10 PM Leif Lindholm <leif@nuviainc.com> wrote:
[...]
> > > > > +FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > > > > +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 21)
> > > > > +FIELD(CCSIDR_EL1, NUMSETS, 32, 24)
> > > >
> > > > The positions and sizes of the ASSOCIATIVITY and NUMSETS CCSIDR fields
> > > > depend on whether the ARMv8.3-CCIDX extension is implemented or not.
> > > > If we really want to define the fields this way, we perhaps should
> > > > define two sets.  Or at the very least, add a comment stating this
> > > > definition is for ARMv8.3-CCIDX.
> > >
> > > Urgh, sorry for this.
> > > I added the fields only to make the CPU definition more readable, so I
> > > think we don't need to worry about runtime handling of this?
> > > But I don't think it makes sense to add only the one form.
> > > Should I use CCIDX_CCSIDR_EL1 for these ones and add
> > >
> > > /* When FEAT_CCIDX is not implemented */
> > > FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > > FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
> > > FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
> > >
> > > with a comment that
> > > /* When FEAT_CCIDX is implemented */
> > > for the former set
> > > ?
> >
> > Having both would be handy, but you need to have different names for
> > the fields.
>
> Different names for the same field?
> I.e.
> FIELD(CCIDX_CCSIDR_EL1, LINESIZE, 0, 3)
> would need a different name for LINESIZE than
> FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> ?

I was thinking about changing the field names, not the register name
because the register is the same, only the layout changes.  So
LINESIZE -> CCIDX_LINESIZE, etc.

That's personal preference, Peter might have a different one.

Thanks,

Laurent
Leif Lindholm Dec. 17, 2020, 12:24 p.m. UTC | #6 
On Thu, Dec 17, 2020 at 13:18:03 +0100, Laurent Desnogues wrote:
> On Thu, Dec 17, 2020 at 1:10 PM Leif Lindholm <leif@nuviainc.com> wrote:
> [...]
> > > > > > +FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > > > > > +FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 21)
> > > > > > +FIELD(CCSIDR_EL1, NUMSETS, 32, 24)
> > > > >
> > > > > The positions and sizes of the ASSOCIATIVITY and NUMSETS CCSIDR fields
> > > > > depend on whether the ARMv8.3-CCIDX extension is implemented or not.
> > > > > If we really want to define the fields this way, we perhaps should
> > > > > define two sets.  Or at the very least, add a comment stating this
> > > > > definition is for ARMv8.3-CCIDX.
> > > >
> > > > Urgh, sorry for this.
> > > > I added the fields only to make the CPU definition more readable, so I
> > > > think we don't need to worry about runtime handling of this?
> > > > But I don't think it makes sense to add only the one form.
> > > > Should I use CCIDX_CCSIDR_EL1 for these ones and add
> > > >
> > > > /* When FEAT_CCIDX is not implemented */
> > > > FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > > > FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
> > > > FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
> > > >
> > > > with a comment that
> > > > /* When FEAT_CCIDX is implemented */
> > > > for the former set
> > > > ?
> > >
> > > Having both would be handy, but you need to have different names for
> > > the fields.
> >
> > Different names for the same field?
> > I.e.
> > FIELD(CCIDX_CCSIDR_EL1, LINESIZE, 0, 3)
> > would need a different name for LINESIZE than
> > FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
> > ?
> 
> I was thinking about changing the field names, not the register name
> because the register is the same, only the layout changes.  So
> LINESIZE -> CCIDX_LINESIZE, etc.
> 
> That's personal preference, Peter might have a different one.

I see. Sure, that works too, and doesn't pollute the register name.
I'll wait for Peter before sending out v3.

Thanks!

/
    Leif

> 
> Thanks,
> 
> Laurent
Peter Maydell Jan. 7, 2021, 5:43 p.m. UTC | #7 
On Thu, 17 Dec 2020 at 12:24, Leif Lindholm <leif@nuviainc.com> wrote:
>
> On Thu, Dec 17, 2020 at 13:18:03 +0100, Laurent Desnogues wrote:
> > I was thinking about changing the field names, not the register name
> > because the register is the same, only the layout changes.  So
> > LINESIZE -> CCIDX_LINESIZE, etc.
> >
> > That's personal preference, Peter might have a different one.
>
> I see. Sure, that works too, and doesn't pollute the register name.
> I'll wait for Peter before sending out v3.

Laurent's suggestion works for me.

thanks
-- PMM
diff mbox series

Patch

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fadd1a47df..90ba707b64 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1736,6 +1736,30 @@  FIELD(V7M_FPCCR, ASPEN, 31, 1)
 /*
  * System register ID fields.
  */
+FIELD(CLIDR_EL1, CTYPE1, 0, 3)
+FIELD(CLIDR_EL1, CTYPE2, 3, 3)
+FIELD(CLIDR_EL1, CTYPE3, 6, 3)
+FIELD(CLIDR_EL1, CTYPE4, 9, 3)
+FIELD(CLIDR_EL1, CTYPE5, 12, 3)
+FIELD(CLIDR_EL1, CTYPE6, 15, 3)
+FIELD(CLIDR_EL1, CTYPE7, 18, 3)
+FIELD(CLIDR_EL1, LOUIS, 21, 3)
+FIELD(CLIDR_EL1, LOC, 24, 3)
+FIELD(CLIDR_EL1, LOUU, 27, 3)
+FIELD(CLIDR_EL1, ICB, 30, 3)
+
+FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
+FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 21)
+FIELD(CCSIDR_EL1, NUMSETS, 32, 24)
+
+FIELD(CTR_EL0,  IMINLINE, 0, 4)
+FIELD(CTR_EL0,  L1IP, 14, 2)
+FIELD(CTR_EL0,  DMINLINE, 16, 4)
+FIELD(CTR_EL0,  ERG, 20, 4)
+FIELD(CTR_EL0,  CWG, 24, 4)
+FIELD(CTR_EL0,  IDC, 28, 1)
+FIELD(CTR_EL0,  DIC, 29, 1)
+
 FIELD(MIDR_EL1, REVISION, 0, 4)
 FIELD(MIDR_EL1, PARTNUM, 4, 12)
 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)