[v2,00/13] Clean up the pll_en_bit from en_mask on all the MediaTek clock drivers

Message

Weiyi Lu Nov. 9, 2020, 2:13 a.m. UTC

This series is based on v5.10-rc1 and
[v5,07/24] clk: mediatek: Fix asymmetrical PLL enable and disable control[1] in Mediatek MT8192 clock support series

[1] https://patchwork.kernel.org/project/linux-mediatek/patch/[e-mail]/

change since v1:
- add patch for MT8167

Weiyi Lu (13):
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT2701
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT2712
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT6765
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT6779
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT6797
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT7622
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT7629
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT8135
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT8167
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT8173
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT8183
  clk: mediatek: Clean up the pll_en_bit from en_mask on MT8516
  clk: mediatek: use en_mask as a pure div_en_mask

 drivers/clk/mediatek/clk-mt2701.c | 26 +++++++++++++-------------
 drivers/clk/mediatek/clk-mt2712.c | 30 +++++++++++++++---------------
 drivers/clk/mediatek/clk-mt6765.c | 20 ++++++++++----------
 drivers/clk/mediatek/clk-mt6779.c | 24 ++++++++++++------------
 drivers/clk/mediatek/clk-mt6797.c | 20 ++++++++++----------
 drivers/clk/mediatek/clk-mt7622.c | 18 +++++++++---------
 drivers/clk/mediatek/clk-mt7629.c | 12 ++++++------
 drivers/clk/mediatek/clk-mt8135.c | 20 ++++++++++----------
 drivers/clk/mediatek/clk-mt8167.c | 16 ++++++++--------
 drivers/clk/mediatek/clk-mt8173.c | 28 ++++++++++++++--------------
 drivers/clk/mediatek/clk-mt8183.c | 22 +++++++++++-----------
 drivers/clk/mediatek/clk-mt8516.c | 12 ++++++------
 drivers/clk/mediatek/clk-pll.c    | 12 ++++--------
 13 files changed, 128 insertions(+), 132 deletions(-)

Comments

Stephen Boyd Dec. 17, 2020, 9:17 a.m. UTC | #1

Quoting Weiyi Lu (2020-11-08 18:13:15)
> This series is based on v5.10-rc1 and
> [v5,07/24] clk: mediatek: Fix asymmetrical PLL enable and disable control[1] in Mediatek MT8192 clock support series
> 
> [1] https://patchwork.kernel.org/project/linux-mediatek/patch/[e-mail]/
> 
> change since v1:
> - add patch for MT8167

The last patch doesn't apply. Also the whole series is base64 encoded
and confuses my MUA. Please resend.