| Message ID | 1603075646-24995-1-git-send-email-igor.druzhinin@citrix.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] x86/intel: insert Ice Lake X (server) model numbers | expand |
On 19.10.2020 04:47, Igor Druzhinin wrote: > LBR, C-state MSRs and if_pschange_mc erratum applicability should correspond > to Ice Lake desktop according to External Design Specification vol.2. > > Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com> > --- > Changes in v2: > - keep partial sorting > > Andrew, since you have access to these documents, please review as you have time. Coming back to this - the recent SDM update inserted at least the model numbers, but besides 6a it also lists 6c. Judging from the majority of additions happening in pairs, I wonder whether we couldn't (reasonably safely) add 6c then here as well. Of course I still can't ack the change either way with access to just the SDM... Jan > --- a/xen/arch/x86/acpi/cpu_idle.c > +++ b/xen/arch/x86/acpi/cpu_idle.c > @@ -181,6 +181,7 @@ static void do_get_hw_residencies(void *arg) > case 0x55: > case 0x5E: > /* Ice Lake */ > + case 0x6A: > case 0x7D: > case 0x7E: > /* Kaby Lake */ > --- a/xen/arch/x86/hvm/vmx/vmx.c > +++ b/xen/arch/x86/hvm/vmx/vmx.c > @@ -2427,6 +2427,7 @@ static bool __init has_if_pschange_mc(void) > case 0x4e: /* Skylake M */ > case 0x5e: /* Skylake D */ > case 0x55: /* Skylake-X / Cascade Lake */ > + case 0x6a: /* Ice Lake-X */ > case 0x7d: /* Ice Lake */ > case 0x7e: /* Ice Lake */ > case 0x8e: /* Kaby / Coffee / Whiskey Lake M */ > @@ -2775,7 +2776,7 @@ static const struct lbr_info *last_branch_msr_get(void) > /* Goldmont Plus */ > case 0x7a: > /* Ice Lake */ > - case 0x7d: case 0x7e: > + case 0x6a: case 0x7d: case 0x7e: > /* Tremont */ > case 0x86: > /* Kaby Lake */ >
On 21/12/2020 16:36, Jan Beulich wrote: > On 19.10.2020 04:47, Igor Druzhinin wrote: >> LBR, C-state MSRs and if_pschange_mc erratum applicability should correspond >> to Ice Lake desktop according to External Design Specification vol.2. >> >> Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com> >> --- >> Changes in v2: >> - keep partial sorting >> >> Andrew, since you have access to these documents, please review as you have time. > > Coming back to this - the recent SDM update inserted at least the > model numbers, but besides 6a it also lists 6c. Judging from the > majority of additions happening in pairs, I wonder whether we > couldn't (reasonably safely) add 6c then here as well. Of course > I still can't ack the change either way with access to just the > SDM... I checked what 0x6c is and it appears to be Ice Lake-D (next gen Xeon D). The information from EDS vol.2 on Ice Lake-D available to us corresponds to what I got for Ice Lake X. So the numbers could be added here as soon as Andrew finds time to review that one. Igor
diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index 27e0b52..eca423c 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -181,6 +181,7 @@ static void do_get_hw_residencies(void *arg) case 0x55: case 0x5E: /* Ice Lake */ + case 0x6A: case 0x7D: case 0x7E: /* Kaby Lake */ diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 86b8916..8382917 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2427,6 +2427,7 @@ static bool __init has_if_pschange_mc(void) case 0x4e: /* Skylake M */ case 0x5e: /* Skylake D */ case 0x55: /* Skylake-X / Cascade Lake */ + case 0x6a: /* Ice Lake-X */ case 0x7d: /* Ice Lake */ case 0x7e: /* Ice Lake */ case 0x8e: /* Kaby / Coffee / Whiskey Lake M */ @@ -2775,7 +2776,7 @@ static const struct lbr_info *last_branch_msr_get(void) /* Goldmont Plus */ case 0x7a: /* Ice Lake */ - case 0x7d: case 0x7e: + case 0x6a: case 0x7d: case 0x7e: /* Tremont */ case 0x86: /* Kaby Lake */
LBR, C-state MSRs and if_pschange_mc erratum applicability should correspond to Ice Lake desktop according to External Design Specification vol.2. Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com> --- Changes in v2: - keep partial sorting Andrew, since you have access to these documents, please review as you have time. --- xen/arch/x86/acpi/cpu_idle.c | 1 + xen/arch/x86/hvm/vmx/vmx.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-)