| Message ID | 20201230115408.492565-3-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | PCI: qcom: fixup PCIe support on sm8250 | expand |
On Wed, Dec 30, 2020 at 02:54:08PM +0300, Dmitry Baryshkov wrote: > On SM8250 additional clock is required for PCIe devices to access NOC. > Update PCIe controller driver to control this clock. > If it is really required then why make it optional? Thanks, Mani > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Fixes: e1dd639e374a ("PCI: qcom: Add SM8250 SoC support") > --- > drivers/pci/controller/dwc/pcie-qcom.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index affa2713bf80..658d007a764c 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -159,8 +159,9 @@ struct qcom_pcie_resources_2_3_3 { > struct reset_control *rst[7]; > }; > > +#define QCOM_PCIE_2_7_0_MAX_CLOCKS 6 > struct qcom_pcie_resources_2_7_0 { > - struct clk_bulk_data clks[6]; > + struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS + 1]; /* + 1 for sf_tbu */ > struct regulator_bulk_data supplies[2]; > struct reset_control *pci_reset; > struct clk *pipe_clk; > @@ -1153,10 +1154,15 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) > res->clks[4].id = "slave_q2a"; > res->clks[5].id = "tbu"; > > - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); > + ret = devm_clk_bulk_get(dev, QCOM_PCIE_2_7_0_MAX_CLOCKS, res->clks); > if (ret < 0) > return ret; > > + /* Optional clock for SM8250 */ > + res->clks[6].clk = devm_clk_get_optional(dev, "ddrss_sf_tbu"); > + if (IS_ERR(res->clks[6].clk)) > + return PTR_ERR(res->clks[6].clk); > + > res->pipe_clk = devm_clk_get(dev, "pipe"); > return PTR_ERR_OR_ZERO(res->pipe_clk); > } > -- > 2.29.2 >
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index affa2713bf80..658d007a764c 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -159,8 +159,9 @@ struct qcom_pcie_resources_2_3_3 { struct reset_control *rst[7]; }; +#define QCOM_PCIE_2_7_0_MAX_CLOCKS 6 struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[6]; + struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS + 1]; /* + 1 for sf_tbu */ struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; struct clk *pipe_clk; @@ -1153,10 +1154,15 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[4].id = "slave_q2a"; res->clks[5].id = "tbu"; - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + ret = devm_clk_bulk_get(dev, QCOM_PCIE_2_7_0_MAX_CLOCKS, res->clks); if (ret < 0) return ret; + /* Optional clock for SM8250 */ + res->clks[6].clk = devm_clk_get_optional(dev, "ddrss_sf_tbu"); + if (IS_ERR(res->clks[6].clk)) + return PTR_ERR(res->clks[6].clk); + res->pipe_clk = devm_clk_get(dev, "pipe"); return PTR_ERR_OR_ZERO(res->pipe_clk); }
On SM8250 additional clock is required for PCIe devices to access NOC. Update PCIe controller driver to control this clock. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: e1dd639e374a ("PCI: qcom: Add SM8250 SoC support") --- drivers/pci/controller/dwc/pcie-qcom.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)