| Message ID | 20201230032314.10042-3-jiaxun.yang@flygoat.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [1/3] MIPS: Add vulnerabilities infrastructure | expand |
Hi, Jiaxun, On Wed, Dec 30, 2020 at 11:26 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote: > > Loongson64C is known to be vulnerable to meltdown according to > PoC from Rui Wang <r@hev.cc>. How about Loongson-3A1000/3B1500, and Loongson-2E/2F? Huacai > > Loongson64G defended these side-channel attack by silicon. > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > arch/mips/kernel/cpu-probe.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c > index 2460783dbdb1..24b21f51353c 100644 > --- a/arch/mips/kernel/cpu-probe.c > +++ b/arch/mips/kernel/cpu-probe.c > @@ -2092,6 +2092,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) > c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | > MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); > c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ > + c->vulnerabilities |= MIPS_VULNBL_MELTDOWN; > + c->vulnerable |= MIPS_VULNBL_MELTDOWN; > break; > case PRID_IMP_LOONGSON_64G: > c->cputype = CPU_LOONGSON64; > @@ -2100,6 +2102,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) > set_isa(c, MIPS_CPU_ISA_M64R2); > decode_cpucfg(c); > c->writecombine = _CACHE_UNCACHED_ACCELERATED; > + c->vulnerabilities |= MIPS_VULNBL_MELTDOWN | > + MIPS_VULNBL_SPECTRE_V1 | MIPS_VULNBL_SPECTRE_V2; > break; > default: > panic("Unknown Loongson Processor ID!"); > -- > 2.30.0 >
Hi Jiaxun, On 12/30/20 11:23 AM, Jiaxun Yang wrote: > Loongson64C is known to be vulnerable to meltdown according to > PoC from Rui Wang <r@hev.cc>. > > Loongson64G defended these side-channel attack by silicon. "Loongson64G mitigated it in hardware"? > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > arch/mips/kernel/cpu-probe.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c > index 2460783dbdb1..24b21f51353c 100644 > --- a/arch/mips/kernel/cpu-probe.c > +++ b/arch/mips/kernel/cpu-probe.c > @@ -2092,6 +2092,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) > c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | > MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); > c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ > + c->vulnerabilities |= MIPS_VULNBL_MELTDOWN; > + c->vulnerable |= MIPS_VULNBL_MELTDOWN; > break; > case PRID_IMP_LOONGSON_64G: > c->cputype = CPU_LOONGSON64; > @@ -2100,6 +2102,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) > set_isa(c, MIPS_CPU_ISA_M64R2); > decode_cpucfg(c); > c->writecombine = _CACHE_UNCACHED_ACCELERATED; > + c->vulnerabilities |= MIPS_VULNBL_MELTDOWN | > + MIPS_VULNBL_SPECTRE_V1 | MIPS_VULNBL_SPECTRE_V2; Of course you forgot to set the "mitigated" mask... Oh wait. It seems the "mitigated" mask in the 1st patch is never used, so either code there or here must be amended. > break; > default: > panic("Unknown Loongson Processor ID!");
在 2020/12/31 23:43, WANG Xuerui 写道: > Hi Jiaxun, > > On 12/30/20 11:23 AM, Jiaxun Yang wrote: >> Loongson64C is known to be vulnerable to meltdown according to >> PoC from Rui Wang <r@hev.cc>. >> >> Loongson64G defended these side-channel attack by silicon. > "Loongson64G mitigated it in hardware"? >> >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> >> --- >> arch/mips/kernel/cpu-probe.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c >> index 2460783dbdb1..24b21f51353c 100644 >> --- a/arch/mips/kernel/cpu-probe.c >> +++ b/arch/mips/kernel/cpu-probe.c >> @@ -2092,6 +2092,8 @@ static inline void cpu_probe_loongson(struct >> cpuinfo_mips *c, unsigned int cpu) >> c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | >> MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); >> c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is >> incomplete */ >> + c->vulnerabilities |= MIPS_VULNBL_MELTDOWN; >> + c->vulnerable |= MIPS_VULNBL_MELTDOWN; >> break; >> case PRID_IMP_LOONGSON_64G: >> c->cputype = CPU_LOONGSON64; >> @@ -2100,6 +2102,8 @@ static inline void cpu_probe_loongson(struct >> cpuinfo_mips *c, unsigned int cpu) >> set_isa(c, MIPS_CPU_ISA_M64R2); >> decode_cpucfg(c); >> c->writecombine = _CACHE_UNCACHED_ACCELERATED; >> + c->vulnerabilities |= MIPS_VULNBL_MELTDOWN | >> + MIPS_VULNBL_SPECTRE_V1 | MIPS_VULNBL_SPECTRE_V2; > > Of course you forgot to set the "mitigated" mask... Oh wait. Hi Xuerui, Actually it belongs to not affected category as there is no action to take in kernel. > > It seems the "mitigated" mask in the 1st patch is never used, so > either code there or here must be amended. Yes, it's just a place holder for future kernel mitigations~ Or I should leave it until we find out these mitigations? Thanks. - Jiaxun > >> break; >> default: >> panic("Unknown Loongson Processor ID!");
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 2460783dbdb1..24b21f51353c 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -2092,6 +2092,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ + c->vulnerabilities |= MIPS_VULNBL_MELTDOWN; + c->vulnerable |= MIPS_VULNBL_MELTDOWN; break; case PRID_IMP_LOONGSON_64G: c->cputype = CPU_LOONGSON64; @@ -2100,6 +2102,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) set_isa(c, MIPS_CPU_ISA_M64R2); decode_cpucfg(c); c->writecombine = _CACHE_UNCACHED_ACCELERATED; + c->vulnerabilities |= MIPS_VULNBL_MELTDOWN | + MIPS_VULNBL_SPECTRE_V1 | MIPS_VULNBL_SPECTRE_V2; break; default: panic("Unknown Loongson Processor ID!");
Loongson64C is known to be vulnerable to meltdown according to PoC from Rui Wang <r@hev.cc>. Loongson64G defended these side-channel attack by silicon. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- arch/mips/kernel/cpu-probe.c | 4 ++++ 1 file changed, 4 insertions(+)