| Message ID | 20201218105708.28480-1-matthias.bgg@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/2] hwrng: iproc-rng200: Fix disable of the block. | expand |
On 2020-12-18 2:57 a.m., matthias.bgg@kernel.org wrote: > From: Matthias Brugger <mbrugger@suse.com> > > When trying to disable the block we bitwise or the control > register with value zero. This is confusing as using bitwise or with > value zero doesn't have any effect at all. Drop this as we already set > the enable bit to zero by appling inverted RNG_RBGEN_MASK. > > Signed-off-by: Matthias Brugger <mbrugger@suse.com> Acked-by: Scott Branden <scott.branden@broadcom.com> > > --- > > Changes in v2: > - fix commit message, dropping Fixes tag > - drop inverted RNT_RBGEN_ENABLE in disable case > > drivers/char/hw_random/iproc-rng200.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/char/hw_random/iproc-rng200.c b/drivers/char/hw_random/iproc-rng200.c > index 01583faf9893..70cd818a0f31 100644 > --- a/drivers/char/hw_random/iproc-rng200.c > +++ b/drivers/char/hw_random/iproc-rng200.c > @@ -28,7 +28,6 @@ > #define RNG_CTRL_OFFSET 0x00 > #define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF > #define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001 > -#define RNG_CTRL_RNG_RBGEN_DISABLE 0x00000000 > > #define RNG_SOFT_RESET_OFFSET 0x04 > #define RNG_SOFT_RESET 0x00000001 > @@ -61,7 +60,6 @@ static void iproc_rng200_restart(void __iomem *rng_base) > /* Disable RBG */ > val = ioread32(rng_base + RNG_CTRL_OFFSET); > val &= ~RNG_CTRL_RNG_RBGEN_MASK; > - val |= RNG_CTRL_RNG_RBGEN_DISABLE; > iowrite32(val, rng_base + RNG_CTRL_OFFSET); > > /* Clear all interrupt status */ > @@ -174,7 +172,6 @@ static void iproc_rng200_cleanup(struct hwrng *rng) > /* Disable RNG hardware */ > val = ioread32(priv->base + RNG_CTRL_OFFSET); > val &= ~RNG_CTRL_RNG_RBGEN_MASK; > - val |= RNG_CTRL_RNG_RBGEN_DISABLE; > iowrite32(val, priv->base + RNG_CTRL_OFFSET); > } >
On 12/18/20 2:57 AM, matthias.bgg@kernel.org wrote: > From: Matthias Brugger <mbrugger@suse.com> > > When trying to disable the block we bitwise or the control > register with value zero. This is confusing as using bitwise or with > value zero doesn't have any effect at all. Drop this as we already set > the enable bit to zero by appling inverted RNG_RBGEN_MASK. > > Signed-off-by: Matthias Brugger <mbrugger@suse.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
On Fri, Dec 18, 2020 at 11:57:07AM +0100, matthias.bgg@kernel.org wrote: > From: Matthias Brugger <mbrugger@suse.com> > > When trying to disable the block we bitwise or the control > register with value zero. This is confusing as using bitwise or with > value zero doesn't have any effect at all. Drop this as we already set > the enable bit to zero by appling inverted RNG_RBGEN_MASK. > > Signed-off-by: Matthias Brugger <mbrugger@suse.com> > > --- > > Changes in v2: > - fix commit message, dropping Fixes tag > - drop inverted RNT_RBGEN_ENABLE in disable case > > drivers/char/hw_random/iproc-rng200.c | 3 --- > 1 file changed, 3 deletions(-) Patch applied. Thanks.
diff --git a/drivers/char/hw_random/iproc-rng200.c b/drivers/char/hw_random/iproc-rng200.c index 01583faf9893..70cd818a0f31 100644 --- a/drivers/char/hw_random/iproc-rng200.c +++ b/drivers/char/hw_random/iproc-rng200.c @@ -28,7 +28,6 @@ #define RNG_CTRL_OFFSET 0x00 #define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF #define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001 -#define RNG_CTRL_RNG_RBGEN_DISABLE 0x00000000 #define RNG_SOFT_RESET_OFFSET 0x04 #define RNG_SOFT_RESET 0x00000001 @@ -61,7 +60,6 @@ static void iproc_rng200_restart(void __iomem *rng_base) /* Disable RBG */ val = ioread32(rng_base + RNG_CTRL_OFFSET); val &= ~RNG_CTRL_RNG_RBGEN_MASK; - val |= RNG_CTRL_RNG_RBGEN_DISABLE; iowrite32(val, rng_base + RNG_CTRL_OFFSET); /* Clear all interrupt status */ @@ -174,7 +172,6 @@ static void iproc_rng200_cleanup(struct hwrng *rng) /* Disable RNG hardware */ val = ioread32(priv->base + RNG_CTRL_OFFSET); val &= ~RNG_CTRL_RNG_RBGEN_MASK; - val |= RNG_CTRL_RNG_RBGEN_DISABLE; iowrite32(val, priv->base + RNG_CTRL_OFFSET); }