| Message ID | 1609557182-20787-3-git-send-email-yilun.xu@intel.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | UIO support for dfl devices | expand |
> Subject: [PATCH v5 2/2] Documentation: fpga: dfl: Add description for DFL > UIO support > > This patch adds description for UIO support for dfl devices on DFL > bus. > > Signed-off-by: Xu Yilun <yilun.xu@intel.com> > --- > v2: no doc in v1, add it for v2. > v3: some documentation fixes. > v4: documentation change since the driver matching is changed. > v5: no change. > --- > Documentation/fpga/dfl.rst | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst > index 0404fe6..b8497f3 100644 > --- a/Documentation/fpga/dfl.rst > +++ b/Documentation/fpga/dfl.rst > @@ -7,6 +7,7 @@ Authors: > - Enno Luebbers <enno.luebbers@intel.com> > - Xiao Guangrong <guangrong.xiao@linux.intel.com> > - Wu Hao <hao.wu@intel.com> > +- Xu Yilun <yilun.xu@intel.com> > > The Device Feature List (DFL) FPGA framework (and drivers according to > this framework) hides the very details of low layer hardwares and provides > @@ -502,6 +503,29 @@ FME Partial Reconfiguration Sub Feature driver (see > drivers/fpga/dfl-fme-pr.c) > could be a reference. > > > +UIO support for DFL devices > +=========================== I think the main purpose is to support userspace driver for DFL devices, and UIO is the option for now. Do you think if the title could be userspace driver support for DFL devices? Hao > +The purpose of an FPGA is to be reprogrammed with newly developed > hardware > +components. New hardware can instantiate a new private feature in the > DFL, and > +then get a DFL device in their system. In some cases users may need a > userspace > +driver for the DFL device: > + > +* Users may need to run some diagnostic test for their hardwares. > +* Users may prototype the kernel driver in user space. > +* Some hardware is designed for specific purposes and does not fit into one > of > + the standard kernel subsystems. > + > +This requires the direct access to the MMIO space and interrupt handling in > +userspace. The dfl-uio-pdev module exposes the UIO device interfaces for > this > +purpose. It adds the uio_pdrv_genirq platform device with the resources of > +the DFL feature, and lets the generic UIO platform device driver provide UIO > +support to userspace. > + > +FPGA_DFL_UIO_PDEV should be selected to enable the dfl-uio-pdev module > driver. > +To support a new DFL feature been directly accessed via UIO, its feature id > +should be added to the driver's id_table. > + > + > Open discussion > =============== > FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial > reconfiguration > -- > 2.7.4
On Mon, Jan 04, 2021 at 12:24:05PM +0800, Wu, Hao wrote: > > Subject: [PATCH v5 2/2] Documentation: fpga: dfl: Add description for DFL > > UIO support > > > > This patch adds description for UIO support for dfl devices on DFL > > bus. > > > > Signed-off-by: Xu Yilun <yilun.xu@intel.com> > > --- > > v2: no doc in v1, add it for v2. > > v3: some documentation fixes. > > v4: documentation change since the driver matching is changed. > > v5: no change. > > --- > > Documentation/fpga/dfl.rst | 24 ++++++++++++++++++++++++ > > 1 file changed, 24 insertions(+) > > > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst > > index 0404fe6..b8497f3 100644 > > --- a/Documentation/fpga/dfl.rst > > +++ b/Documentation/fpga/dfl.rst > > @@ -7,6 +7,7 @@ Authors: > > - Enno Luebbers <enno.luebbers@intel.com> > > - Xiao Guangrong <guangrong.xiao@linux.intel.com> > > - Wu Hao <hao.wu@intel.com> > > +- Xu Yilun <yilun.xu@intel.com> > > > > The Device Feature List (DFL) FPGA framework (and drivers according to > > this framework) hides the very details of low layer hardwares and provides > > @@ -502,6 +503,29 @@ FME Partial Reconfiguration Sub Feature driver (see > > drivers/fpga/dfl-fme-pr.c) > > could be a reference. > > > > > > +UIO support for DFL devices > > +=========================== > > I think the main purpose is to support userspace driver for DFL devices, and > UIO is the option for now. Do you think if the title could be userspace driver > support for DFL devices? Yes, I could change it. Thanks, Yilun
On 1/1/21 7:13 PM, Xu Yilun wrote: > This patch adds description for UIO support for dfl devices on DFL > bus. > > Signed-off-by: Xu Yilun <yilun.xu@intel.com> > --- > v2: no doc in v1, add it for v2. > v3: some documentation fixes. > v4: documentation change since the driver matching is changed. > v5: no change. > --- > Documentation/fpga/dfl.rst | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst > index 0404fe6..b8497f3 100644 > --- a/Documentation/fpga/dfl.rst > +++ b/Documentation/fpga/dfl.rst > @@ -7,6 +7,7 @@ Authors: > - Enno Luebbers <enno.luebbers@intel.com> > - Xiao Guangrong <guangrong.xiao@linux.intel.com> > - Wu Hao <hao.wu@intel.com> > +- Xu Yilun <yilun.xu@intel.com> > > The Device Feature List (DFL) FPGA framework (and drivers according to > this framework) hides the very details of low layer hardwares and provides > @@ -502,6 +503,29 @@ FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) > could be a reference. > > > +UIO support for DFL devices > +=========================== > +The purpose of an FPGA is to be reprogrammed with newly developed hardware > +components. New hardware can instantiate a new private feature in the DFL, and > +then get a DFL device in their system. In some cases users may need a userspace > +driver for the DFL device: > + > +* Users may need to run some diagnostic test for their hardwares. > +* Users may prototype the kernel driver in user space. > +* Some hardware is designed for specific purposes and does not fit into one of > + the standard kernel subsystems. > + > +This requires the direct access to the MMIO space and interrupt handling in This may be better stated as: "This requires direct access to MMIO space and interrupt handling from userspace." - Russ > +userspace. The dfl-uio-pdev module exposes the UIO device interfaces for this > +purpose. It adds the uio_pdrv_genirq platform device with the resources of > +the DFL feature, and lets the generic UIO platform device driver provide UIO > +support to userspace. > + > +FPGA_DFL_UIO_PDEV should be selected to enable the dfl-uio-pdev module driver. > +To support a new DFL feature been directly accessed via UIO, its feature id > +should be added to the driver's id_table. > + > + > Open discussion > =============== > FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration
On Mon, Jan 04, 2021 at 09:19:24AM -0800, Russ Weight wrote: > > > On 1/1/21 7:13 PM, Xu Yilun wrote: > > This patch adds description for UIO support for dfl devices on DFL > > bus. > > > > Signed-off-by: Xu Yilun <yilun.xu@intel.com> > > --- > > v2: no doc in v1, add it for v2. > > v3: some documentation fixes. > > v4: documentation change since the driver matching is changed. > > v5: no change. > > --- > > Documentation/fpga/dfl.rst | 24 ++++++++++++++++++++++++ > > 1 file changed, 24 insertions(+) > > > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst > > index 0404fe6..b8497f3 100644 > > --- a/Documentation/fpga/dfl.rst > > +++ b/Documentation/fpga/dfl.rst > > @@ -7,6 +7,7 @@ Authors: > > - Enno Luebbers <enno.luebbers@intel.com> > > - Xiao Guangrong <guangrong.xiao@linux.intel.com> > > - Wu Hao <hao.wu@intel.com> > > +- Xu Yilun <yilun.xu@intel.com> > > > > The Device Feature List (DFL) FPGA framework (and drivers according to > > this framework) hides the very details of low layer hardwares and provides > > @@ -502,6 +503,29 @@ FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) > > could be a reference. > > > > > > +UIO support for DFL devices > > +=========================== > > +The purpose of an FPGA is to be reprogrammed with newly developed hardware > > +components. New hardware can instantiate a new private feature in the DFL, and > > +then get a DFL device in their system. In some cases users may need a userspace > > +driver for the DFL device: > > + > > +* Users may need to run some diagnostic test for their hardwares. > > +* Users may prototype the kernel driver in user space. > > +* Some hardware is designed for specific purposes and does not fit into one of > > + the standard kernel subsystems. > > + > > +This requires the direct access to the MMIO space and interrupt handling in > This may be better stated as: > > "This requires direct access to MMIO space and interrupt handling from userspace." Thanks for the correction, I'll change it. Yilun
diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index 0404fe6..b8497f3 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -7,6 +7,7 @@ Authors: - Enno Luebbers <enno.luebbers@intel.com> - Xiao Guangrong <guangrong.xiao@linux.intel.com> - Wu Hao <hao.wu@intel.com> +- Xu Yilun <yilun.xu@intel.com> The Device Feature List (DFL) FPGA framework (and drivers according to this framework) hides the very details of low layer hardwares and provides @@ -502,6 +503,29 @@ FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) could be a reference. +UIO support for DFL devices +=========================== +The purpose of an FPGA is to be reprogrammed with newly developed hardware +components. New hardware can instantiate a new private feature in the DFL, and +then get a DFL device in their system. In some cases users may need a userspace +driver for the DFL device: + +* Users may need to run some diagnostic test for their hardwares. +* Users may prototype the kernel driver in user space. +* Some hardware is designed for specific purposes and does not fit into one of + the standard kernel subsystems. + +This requires the direct access to the MMIO space and interrupt handling in +userspace. The dfl-uio-pdev module exposes the UIO device interfaces for this +purpose. It adds the uio_pdrv_genirq platform device with the resources of +the DFL feature, and lets the generic UIO platform device driver provide UIO +support to userspace. + +FPGA_DFL_UIO_PDEV should be selected to enable the dfl-uio-pdev module driver. +To support a new DFL feature been directly accessed via UIO, its feature id +should be added to the driver's id_table. + + Open discussion =============== FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration
This patch adds description for UIO support for dfl devices on DFL bus. Signed-off-by: Xu Yilun <yilun.xu@intel.com> --- v2: no doc in v1, add it for v2. v3: some documentation fixes. v4: documentation change since the driver matching is changed. v5: no change. --- Documentation/fpga/dfl.rst | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)