| Message ID | 20210111151704.26296-2-max.krummenacher@toradex.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/1] ARM: imx: build suspend-imx6.S with arm instruction set | expand |
On Mon, Jan 11, 2021 at 5:20 PM Max Krummenacher <max.oss.09@gmail.com> wrote: > > When the kernel is configured to use the Thumb-2 instruction set > "suspend-to-memory" fails to resume. Observed on a Colibri iMX6ULL > (i.MX 6ULL) and Apalis iMX6 (i.MX 6Q). > > It looks like the CPU resumes unconditionally in ARM instruction mode > and then chokes on the presented Thumb-2 code it should execute. > > Fix this by using the arm instruction set for all code in > suspend-imx6.S. > > Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> > > --- > > arch/arm/mach-imx/suspend-imx6.S | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S > index 1eabf2d2834be..e06f946b75b96 100644 > --- a/arch/arm/mach-imx/suspend-imx6.S > +++ b/arch/arm/mach-imx/suspend-imx6.S > @@ -67,6 +67,7 @@ > #define MX6Q_CCM_CCR 0x0 > > .align 3 > + .arm > > .macro sync_l2_cache > > -- > 2.26.2 >
On 11.01.21 16:17, Max Krummenacher wrote: > When the kernel is configured to use the Thumb-2 instruction set > "suspend-to-memory" fails to resume. Observed on a Colibri iMX6ULL > (i.MX 6ULL) and Apalis iMX6 (i.MX 6Q). > > It looks like the CPU resumes unconditionally in ARM instruction mode > and then chokes on the presented Thumb-2 code it should execute. > > Fix this by using the arm instruction set for all code in > suspend-imx6.S. > > Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> > > --- > > arch/arm/mach-imx/suspend-imx6.S | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S > index 1eabf2d2834be..e06f946b75b96 100644 > --- a/arch/arm/mach-imx/suspend-imx6.S > +++ b/arch/arm/mach-imx/suspend-imx6.S > @@ -67,6 +67,7 @@ > #define MX6Q_CCM_CCR 0x0 > > .align 3 > + .arm You had a return to thumb at the end of this subroutine in the cover letter, yet here it's omitted. Why? > > .macro sync_l2_cache > >
Resent due to gmail adding HTML, sorry for the noise. Am Montag, den 11.01.2021, 18:49 +0100 schrieb Ahmad Fatoum: > > On 11.01.21 16:17, Max Krummenacher wrote: > > When the kernel is configured to use the Thumb-2 instruction set > > "suspend-to-memory" fails to resume. Observed on a Colibri iMX6ULL > > (i.MX 6ULL) and Apalis iMX6 (i.MX 6Q). > > > > It looks like the CPU resumes unconditionally in ARM instruction mode > > and then chokes on the presented Thumb-2 code it should execute. > > > > Fix this by using the arm instruction set for all code in > > suspend-imx6.S. > > > > Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> > > > > --- > > > > arch/arm/mach-imx/suspend-imx6.S | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S > > index 1eabf2d2834be..e06f946b75b96 100644 > > --- a/arch/arm/mach-imx/suspend-imx6.S > > +++ b/arch/arm/mach-imx/suspend-imx6.S > > @@ -67,6 +67,7 @@ > > #define MX6Q_CCM_CCR 0x0 > > > > .align 3 > > + .arm > > You had a return to thumb at the end of this subroutine in the cover letter, > yet here it's omitted. Why? Now the whole subroutine is compiled for ARM and the return address has bit 0 set so that on jumping back to the caller the CPU will switch back to Thumb-2. Probably the return to Thumb-2 isn't needed in the cover letter solution and it would also work to finish the subroutine in ARM instruction set. However it looks strange to me if a function which begins with the ARM instruction set would come to the return in Thumb-2. > > > > > .macro sync_l2_cache > > > >
On Mon, Jan 11, 2021 at 04:17:04PM +0100, Max Krummenacher wrote: > When the kernel is configured to use the Thumb-2 instruction set > "suspend-to-memory" fails to resume. Observed on a Colibri iMX6ULL > (i.MX 6ULL) and Apalis iMX6 (i.MX 6Q). > > It looks like the CPU resumes unconditionally in ARM instruction mode > and then chokes on the presented Thumb-2 code it should execute. > > Fix this by using the arm instruction set for all code in > suspend-imx6.S. > > Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Applied, thanks.
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S index 1eabf2d2834be..e06f946b75b96 100644 --- a/arch/arm/mach-imx/suspend-imx6.S +++ b/arch/arm/mach-imx/suspend-imx6.S @@ -67,6 +67,7 @@ #define MX6Q_CCM_CCR 0x0 .align 3 + .arm .macro sync_l2_cache
When the kernel is configured to use the Thumb-2 instruction set "suspend-to-memory" fails to resume. Observed on a Colibri iMX6ULL (i.MX 6ULL) and Apalis iMX6 (i.MX 6Q). It looks like the CPU resumes unconditionally in ARM instruction mode and then chokes on the presented Thumb-2 code it should execute. Fix this by using the arm instruction set for all code in suspend-imx6.S. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> --- arch/arm/mach-imx/suspend-imx6.S | 1 + 1 file changed, 1 insertion(+)