diff mbox series

[3/4] ARM: dts: imx6sl-tolino-shine3: correct console uart pinmux

Message ID 20210112231549.29957-5-andreas@kemnade.info (mailing list archive)
State New, archived
Headers show
Series None | expand

Commit Message

Andreas Kemnade Jan. 12, 2021, 11:15 p.m. UTC
Configuration was correct enough to work with the pre-configuration done by
uboot. While at it, also document the location.

Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
---
 arch/arm/boot/dts/imx6sl-tolino-shine3.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

H. Nikolaus Schaller Jan. 13, 2021, 12:40 p.m. UTC | #1
Ah, there is a v2. Let's hope this gets merged/processed by robots correctly :)

> Am 13.01.2021 um 00:15 schrieb Andreas Kemnade <andreas@kemnade.info>:
> 
> Configuration was correct enough to work with the pre-configuration done by
> uboot. While at it, also document the location.
> 
> Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
> ---
> arch/arm/boot/dts/imx6sl-tolino-shine3.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine3.dts b/arch/arm/boot/dts/imx6sl-tolino-shine3.dts
> index 27143ea0f0f1..62d2ebda04ff 100644
> --- a/arch/arm/boot/dts/imx6sl-tolino-shine3.dts
> +++ b/arch/arm/boot/dts/imx6sl-tolino-shine3.dts
> @@ -156,7 +156,7 @@
> 	pinctrl_uart1: uart1grp {
> 		fsl,pins = <
> 			MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
> -			MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x1b0b1
> +			MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
> 		>;
> 	};
> 
> -- 
> 2.20.1
> 
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diff mbox series

Patch

diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine3.dts b/arch/arm/boot/dts/imx6sl-tolino-shine3.dts
index 27143ea0f0f1..62d2ebda04ff 100644
--- a/arch/arm/boot/dts/imx6sl-tolino-shine3.dts
+++ b/arch/arm/boot/dts/imx6sl-tolino-shine3.dts
@@ -156,7 +156,7 @@ 
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
-			MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x1b0b1
+			MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
 		>;
 	};