diff mbox series

[RFC,3/4] hw/intc: set GICD_TYPER.DVIS for GICv4

Message ID 20210124025306.3949-4-leif@nuviainc.com (mailing list archive)
State New, archived
Headers show
Series hw/intc: enable GICv4 memory layout for GICv3 driver | expand

Commit Message

Leif Lindholm Jan. 24, 2021, 2:53 a.m. UTC
The VLPI frames are what make the redistributor size change, so ensure
we state in GICD_TYPER that we have them.

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
---
 hw/intc/arm_gicv3_dist.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Peter Maydell Feb. 2, 2021, 10:34 a.m. UTC | #1
On Sun, 24 Jan 2021 at 02:53, Leif Lindholm <leif@nuviainc.com> wrote:
>
> The VLPI frames are what make the redistributor size change, so ensure
> we state in GICD_TYPER that we have them.
>
> Signed-off-by: Leif Lindholm <leif@nuviainc.com>
> ---
>  hw/intc/arm_gicv3_dist.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
> index b65f56f903..833deb0a74 100644
> --- a/hw/intc/arm_gicv3_dist.c
> +++ b/hw/intc/arm_gicv3_dist.c
> @@ -387,6 +387,9 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
>
>          *data = (1 << 25) | (1 << 24) | (sec_extn << 10) |
>              (0xf << 19) | itlinesnumber;
> +        if (s->revision == 4) {
> +            *data |= (1 << 18);;
> +        }

Double semicolon.

>          return MEMTX_OK;
>      }
>      case GICD_IIDR:

I think I'd prefer not to take this patch in mainline for the moment:
it would be "safe", in the sense that it doesn't affect anything,
but it's not the only thing in this register that changes for GIC
versions > 3, and it would make a lot more sense to go in as part
of the general support for the feature the bit is advertising.

thanks
-- PMM
diff mbox series

Patch

diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index b65f56f903..833deb0a74 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -387,6 +387,9 @@  static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
 
         *data = (1 << 25) | (1 << 24) | (sec_extn << 10) |
             (0xf << 19) | itlinesnumber;
+        if (s->revision == 4) {
+            *data |= (1 << 18);;
+        }
         return MEMTX_OK;
     }
     case GICD_IIDR: