| Message ID | 1612685964-21890-4-git-send-email-stefanc@marvell.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | net: mvpp2: Add TX Flow Control support | expand |
Hi Stefan, On Sun, Feb 07 2021, stefanc@marvell.com wrote: > From: Stefan Chulski <stefanc@marvell.com> > > This patch adds CM3 memory map and CM3 read/write callbacks. > No functionality changes. > > Signed-off-by: Stefan Chulski <stefanc@marvell.com> > --- > drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 7 +++ > drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 63 +++++++++++++++++++- > 2 files changed, 67 insertions(+), 3 deletions(-) > > diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > index 6bd7e40..aec9179 100644 > --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > @@ -748,6 +748,9 @@ > #define MVPP2_TX_FIFO_THRESHOLD(kb) \ > ((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) > > +/* MSS Flow control */ > +#define MSS_SRAM_SIZE 0x800 > + > /* RX buffer constants */ > #define MVPP2_SKB_SHINFO_SIZE \ > SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) > @@ -925,6 +928,7 @@ struct mvpp2 { > /* Shared registers' base addresses */ > void __iomem *lms_base; > void __iomem *iface_base; > + void __iomem *cm3_base; > > /* On PPv2.2, each "software thread" can access the base > * register through a separate address space, each 64 KB apart > @@ -996,6 +1000,9 @@ struct mvpp2 { > > /* page_pool allocator */ > struct page_pool *page_pool[MVPP2_PORT_MAX_RXQ]; > + > + /* CM3 SRAM pool */ > + struct gen_pool *sram_pool; > }; > > struct mvpp2_pcpu_stats { > diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > index a07cf60..307f9fd 100644 > --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > @@ -25,6 +25,7 @@ > #include <linux/of_net.h> > #include <linux/of_address.h> > #include <linux/of_device.h> > +#include <linux/genalloc.h> > #include <linux/phy.h> > #include <linux/phylink.h> > #include <linux/phy/phy.h> > @@ -6846,6 +6847,44 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) > return 0; > } > > +static int mvpp2_get_sram(struct platform_device *pdev, > + struct mvpp2 *priv) > +{ > + struct device_node *dn = pdev->dev.of_node; > + static bool defer_once; > + struct resource *res; > + > + if (has_acpi_companion(&pdev->dev)) { > + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); > + if (!res) { > + dev_warn(&pdev->dev, "ACPI is too old, Flow control not supported\n"); > + return 0; > + } > + priv->cm3_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(priv->cm3_base)) > + return PTR_ERR(priv->cm3_base); > + } else { > + priv->sram_pool = of_gen_pool_get(dn, "cm3-mem", 0); > + if (!priv->sram_pool) { > + if (!defer_once) { > + defer_once = true; > + /* Try defer once */ > + return -EPROBE_DEFER; > + } > + dev_warn(&pdev->dev, "DT is too old, Flow control not supported\n"); This warning will show on every DT system with no cm3-mem property, right? > + return -ENOMEM; > + } > + /* cm3_base allocated with offset zero into the SRAM since mapping size > + * is equal to requested size. > + */ > + priv->cm3_base = (void __iomem *)gen_pool_alloc(priv->sram_pool, > + MSS_SRAM_SIZE); > + if (!priv->cm3_base) > + return -ENOMEM; > + } > + return 0; > +} > + > static int mvpp2_probe(struct platform_device *pdev) > { > const struct acpi_device_id *acpi_id; > @@ -6902,6 +6941,13 @@ static int mvpp2_probe(struct platform_device *pdev) > priv->iface_base = devm_ioremap_resource(&pdev->dev, res); > if (IS_ERR(priv->iface_base)) > return PTR_ERR(priv->iface_base); > + > + /* Map CM3 SRAM */ > + err = mvpp2_get_sram(pdev, priv); > + if (err == -EPROBE_DEFER) > + return err; > + else if (err) > + dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n"); This one will show as well. I would not expect that from a patch that makes "no functional change". baruch > } > > if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) { > @@ -6947,11 +6993,13 @@ static int mvpp2_probe(struct platform_device *pdev) > > if (dev_of_node(&pdev->dev)) { > priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); > - if (IS_ERR(priv->pp_clk)) > - return PTR_ERR(priv->pp_clk); > + if (IS_ERR(priv->pp_clk)) { > + err = PTR_ERR(priv->pp_clk); > + goto err_cm3; > + } > err = clk_prepare_enable(priv->pp_clk); > if (err < 0) > - return err; > + goto err_cm3; > > priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); > if (IS_ERR(priv->gop_clk)) { > @@ -7087,6 +7135,11 @@ static int mvpp2_probe(struct platform_device *pdev) > clk_disable_unprepare(priv->gop_clk); > err_pp_clk: > clk_disable_unprepare(priv->pp_clk); > +err_cm3: > + if (priv->sram_pool && priv->cm3_base) > + gen_pool_free(priv->sram_pool, (unsigned long)priv->cm3_base, > + MSS_SRAM_SIZE); > + > return err; > } > > @@ -7127,6 +7180,10 @@ static int mvpp2_remove(struct platform_device *pdev) > aggr_txq->descs_dma); > } > > + if (priv->sram_pool && priv->cm3_base) > + gen_pool_free(priv->sram_pool, (unsigned long)priv->cm3_base, > + MSS_SRAM_SIZE); > + > if (is_acpi_node(port_fwnode)) > return 0;
> > } > > > > +static int mvpp2_get_sram(struct platform_device *pdev, > > + struct mvpp2 *priv) > > +{ > > + struct device_node *dn = pdev->dev.of_node; > > + static bool defer_once; > > + struct resource *res; > > + > > + if (has_acpi_companion(&pdev->dev)) { > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); > > + if (!res) { > > + dev_warn(&pdev->dev, "ACPI is too old, Flow control > not supported\n"); > > + return 0; > > + } > > + priv->cm3_base = devm_ioremap_resource(&pdev->dev, > res); > > + if (IS_ERR(priv->cm3_base)) > > + return PTR_ERR(priv->cm3_base); > > + } else { > > + priv->sram_pool = of_gen_pool_get(dn, "cm3-mem", 0); > > + if (!priv->sram_pool) { > > + if (!defer_once) { > > + defer_once = true; > > + /* Try defer once */ > > + return -EPROBE_DEFER; > > + } > > + dev_warn(&pdev->dev, "DT is too old, Flow control > not > > +supported\n"); > > This warning will show on every DT system with no cm3-mem property, > right? > All DT system would has cm3-mem property if " add CM3 SRAM memory to cp11x ethernet device tree " patch applied. This is also only warning message, without any functional impact. Regards, Stefan.
On Sun, Feb 07, 2021 at 10:19:12AM +0200, stefanc@marvell.com wrote: > From: Stefan Chulski <stefanc@marvell.com> > > This patch adds CM3 memory map and CM3 read/write callbacks. > No functionality changes. > > Signed-off-by: Stefan Chulski <stefanc@marvell.com> > --- > drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 7 +++ > drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 63 +++++++++++++++++++- > 2 files changed, 67 insertions(+), 3 deletions(-) > > diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > index 6bd7e40..aec9179 100644 > --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h > @@ -748,6 +748,9 @@ > #define MVPP2_TX_FIFO_THRESHOLD(kb) \ > ((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) > > +/* MSS Flow control */ > +#define MSS_SRAM_SIZE 0x800 > + > /* RX buffer constants */ > #define MVPP2_SKB_SHINFO_SIZE \ > SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) > @@ -925,6 +928,7 @@ struct mvpp2 { > /* Shared registers' base addresses */ > void __iomem *lms_base; > void __iomem *iface_base; > + void __iomem *cm3_base; > > /* On PPv2.2, each "software thread" can access the base > * register through a separate address space, each 64 KB apart > @@ -996,6 +1000,9 @@ struct mvpp2 { > > /* page_pool allocator */ > struct page_pool *page_pool[MVPP2_PORT_MAX_RXQ]; > + > + /* CM3 SRAM pool */ > + struct gen_pool *sram_pool; > }; > > struct mvpp2_pcpu_stats { > diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > index a07cf60..307f9fd 100644 > --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c > @@ -25,6 +25,7 @@ > #include <linux/of_net.h> > #include <linux/of_address.h> > #include <linux/of_device.h> > +#include <linux/genalloc.h> > #include <linux/phy.h> > #include <linux/phylink.h> > #include <linux/phy/phy.h> > @@ -6846,6 +6847,44 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) > return 0; > } > > +static int mvpp2_get_sram(struct platform_device *pdev, > + struct mvpp2 *priv) > +{ > + struct device_node *dn = pdev->dev.of_node; > + static bool defer_once; > + struct resource *res; > + > + if (has_acpi_companion(&pdev->dev)) { > + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); > + if (!res) { > + dev_warn(&pdev->dev, "ACPI is too old, Flow control not supported\n"); > + return 0; > + } > + priv->cm3_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(priv->cm3_base)) > + return PTR_ERR(priv->cm3_base); > + } else { > + priv->sram_pool = of_gen_pool_get(dn, "cm3-mem", 0); > + if (!priv->sram_pool) { > + if (!defer_once) { > + defer_once = true; > + /* Try defer once */ > + return -EPROBE_DEFER; > + } > + dev_warn(&pdev->dev, "DT is too old, Flow control not supported\n"); > + return -ENOMEM; > + } > + /* cm3_base allocated with offset zero into the SRAM since mapping size > + * is equal to requested size. > + */ > + priv->cm3_base = (void __iomem *)gen_pool_alloc(priv->sram_pool, > + MSS_SRAM_SIZE); > + if (!priv->cm3_base) > + return -ENOMEM; > + } For v2 i asked: > I'm wondering if using a pool even makes sense. The ACPI case just > ioremap() the memory region. Either this memory is dedicated, and > then there is no need to use a pool, or the memory is shared, and at > some point the ACPI code is going to run into problems when some > other driver also wants access. There was never an answer to this. Also, the defer_once stuff is odd. You don't see any other driver do this. The core decides when to give up probing a device. This is partially an API problem. of_gen_pool_get() gives you no idea why it failed. Is the property missing, or has the SRAM not probed yet. If the answer to my question is yes, a pool does make sense, it would be good to add an of_gen_pool_get_optional() which returns ERR_PTR(-EPROBE_DEFER) if the property is in DT, but is not yet available, NULL if the properties does not exist, and a pointer if everything goes well. Andrew
> > + priv->sram_pool = of_gen_pool_get(dn, "cm3-mem", 0); > > + if (!priv->sram_pool) { > > + if (!defer_once) { > > + defer_once = true; > > + /* Try defer once */ > > + return -EPROBE_DEFER; > > + } > > + dev_warn(&pdev->dev, "DT is too old, Flow control > not supported\n"); > > + return -ENOMEM; > > + } > > + /* cm3_base allocated with offset zero into the SRAM since > mapping size > > + * is equal to requested size. > > + */ > > + priv->cm3_base = (void __iomem *)gen_pool_alloc(priv- > >sram_pool, > > + > MSS_SRAM_SIZE); > > + if (!priv->cm3_base) > > + return -ENOMEM; > > + } > > For v2 i asked: > > > I'm wondering if using a pool even makes sense. The ACPI case just > > ioremap() the memory region. Either this memory is dedicated, and then > > there is no need to use a pool, or the memory is shared, and at some > > point the ACPI code is going to run into problems when some other > > driver also wants access. > > There was never an answer to this. Sorry probably missed this. Currently this memory not shared and I can just ioremap same way as in ACPI case. In this case I can remove EPROBE_DEFER. Thanks, Stefan.
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h index 6bd7e40..aec9179 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h @@ -748,6 +748,9 @@ #define MVPP2_TX_FIFO_THRESHOLD(kb) \ ((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) +/* MSS Flow control */ +#define MSS_SRAM_SIZE 0x800 + /* RX buffer constants */ #define MVPP2_SKB_SHINFO_SIZE \ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) @@ -925,6 +928,7 @@ struct mvpp2 { /* Shared registers' base addresses */ void __iomem *lms_base; void __iomem *iface_base; + void __iomem *cm3_base; /* On PPv2.2, each "software thread" can access the base * register through a separate address space, each 64 KB apart @@ -996,6 +1000,9 @@ struct mvpp2 { /* page_pool allocator */ struct page_pool *page_pool[MVPP2_PORT_MAX_RXQ]; + + /* CM3 SRAM pool */ + struct gen_pool *sram_pool; }; struct mvpp2_pcpu_stats { diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c index a07cf60..307f9fd 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c @@ -25,6 +25,7 @@ #include <linux/of_net.h> #include <linux/of_address.h> #include <linux/of_device.h> +#include <linux/genalloc.h> #include <linux/phy.h> #include <linux/phylink.h> #include <linux/phy/phy.h> @@ -6846,6 +6847,44 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) return 0; } +static int mvpp2_get_sram(struct platform_device *pdev, + struct mvpp2 *priv) +{ + struct device_node *dn = pdev->dev.of_node; + static bool defer_once; + struct resource *res; + + if (has_acpi_companion(&pdev->dev)) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (!res) { + dev_warn(&pdev->dev, "ACPI is too old, Flow control not supported\n"); + return 0; + } + priv->cm3_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(priv->cm3_base)) + return PTR_ERR(priv->cm3_base); + } else { + priv->sram_pool = of_gen_pool_get(dn, "cm3-mem", 0); + if (!priv->sram_pool) { + if (!defer_once) { + defer_once = true; + /* Try defer once */ + return -EPROBE_DEFER; + } + dev_warn(&pdev->dev, "DT is too old, Flow control not supported\n"); + return -ENOMEM; + } + /* cm3_base allocated with offset zero into the SRAM since mapping size + * is equal to requested size. + */ + priv->cm3_base = (void __iomem *)gen_pool_alloc(priv->sram_pool, + MSS_SRAM_SIZE); + if (!priv->cm3_base) + return -ENOMEM; + } + return 0; +} + static int mvpp2_probe(struct platform_device *pdev) { const struct acpi_device_id *acpi_id; @@ -6902,6 +6941,13 @@ static int mvpp2_probe(struct platform_device *pdev) priv->iface_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(priv->iface_base)) return PTR_ERR(priv->iface_base); + + /* Map CM3 SRAM */ + err = mvpp2_get_sram(pdev, priv); + if (err == -EPROBE_DEFER) + return err; + else if (err) + dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n"); } if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) { @@ -6947,11 +6993,13 @@ static int mvpp2_probe(struct platform_device *pdev) if (dev_of_node(&pdev->dev)) { priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); - if (IS_ERR(priv->pp_clk)) - return PTR_ERR(priv->pp_clk); + if (IS_ERR(priv->pp_clk)) { + err = PTR_ERR(priv->pp_clk); + goto err_cm3; + } err = clk_prepare_enable(priv->pp_clk); if (err < 0) - return err; + goto err_cm3; priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); if (IS_ERR(priv->gop_clk)) { @@ -7087,6 +7135,11 @@ static int mvpp2_probe(struct platform_device *pdev) clk_disable_unprepare(priv->gop_clk); err_pp_clk: clk_disable_unprepare(priv->pp_clk); +err_cm3: + if (priv->sram_pool && priv->cm3_base) + gen_pool_free(priv->sram_pool, (unsigned long)priv->cm3_base, + MSS_SRAM_SIZE); + return err; } @@ -7127,6 +7180,10 @@ static int mvpp2_remove(struct platform_device *pdev) aggr_txq->descs_dma); } + if (priv->sram_pool && priv->cm3_base) + gen_pool_free(priv->sram_pool, (unsigned long)priv->cm3_base, + MSS_SRAM_SIZE); + if (is_acpi_node(port_fwnode)) return 0;