| Message ID | 20210208014221.196584-2-jitao.shi@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add check for max clock rate in mode_valid | expand |
Hi, Jitao: Jitao Shi <jitao.shi@mediatek.com> 於 2021年2月8日 週一 上午9:42寫道： > > Add per-platform max clock rate check in mtk_dpi_bridge_mode_valid. Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 52f11a63a330..ffa4a0f1989f 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -118,6 +118,7 @@ struct mtk_dpi_yc_limit { > struct mtk_dpi_conf { > unsigned int (*cal_factor)(int clock); > u32 reg_h_fre_con; > + u32 max_clock_khz; > bool edge_sel_en; > }; > > @@ -555,9 +556,22 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) > mtk_dpi_set_display_mode(dpi, &dpi->mode); > } > > +static enum drm_mode_status > +mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, > + const struct drm_display_mode *mode) > +{ > + struct mtk_dpi *dpi = bridge_to_dpi(bridge); > + > + if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz) > + return MODE_CLOCK_HIGH; > + > + return MODE_OK; > +} > + > static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { > .attach = mtk_dpi_bridge_attach, > .mode_set = mtk_dpi_bridge_mode_set, > + .mode_valid = mtk_dpi_bridge_mode_valid, > .disable = mtk_dpi_bridge_disable, > .enable = mtk_dpi_bridge_enable, > }; > @@ -673,17 +687,20 @@ static unsigned int mt8183_calculate_factor(int clock) > static const struct mtk_dpi_conf mt8173_conf = { > .cal_factor = mt8173_calculate_factor, > .reg_h_fre_con = 0xe0, > + .max_clock_khz = 300000, > }; > > static const struct mtk_dpi_conf mt2701_conf = { > .cal_factor = mt2701_calculate_factor, > .reg_h_fre_con = 0xb0, > .edge_sel_en = true, > + .max_clock_khz = 150000, > }; > > static const struct mtk_dpi_conf mt8183_conf = { > .cal_factor = mt8183_calculate_factor, > .reg_h_fre_con = 0xe0, > + .max_clock_khz = 100000, > }; > > static int mtk_dpi_probe(struct platform_device *pdev) > -- > 2.25.1
+Pi-Hsun Shih On Mon, Feb 8, 2021 at 9:42 AM Jitao Shi <jitao.shi@mediatek.com> wrote: > > Add per-platform max clock rate check in mtk_dpi_bridge_mode_valid. > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> I believe this patch (and the following) were actually authored by Pi-Hsun: https://crrev.com/c/2628812 . Would be best to keep the author information (unless I'm missing something of course). > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 52f11a63a330..ffa4a0f1989f 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -118,6 +118,7 @@ struct mtk_dpi_yc_limit { > struct mtk_dpi_conf { > unsigned int (*cal_factor)(int clock); > u32 reg_h_fre_con; > + u32 max_clock_khz; > bool edge_sel_en; > }; > > @@ -555,9 +556,22 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) > mtk_dpi_set_display_mode(dpi, &dpi->mode); > } > > +static enum drm_mode_status > +mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, > + const struct drm_display_mode *mode) > +{ > + struct mtk_dpi *dpi = bridge_to_dpi(bridge); > + > + if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz) > + return MODE_CLOCK_HIGH; > + > + return MODE_OK; > +} > + > static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { > .attach = mtk_dpi_bridge_attach, > .mode_set = mtk_dpi_bridge_mode_set, > + .mode_valid = mtk_dpi_bridge_mode_valid, > .disable = mtk_dpi_bridge_disable, > .enable = mtk_dpi_bridge_enable, > }; > @@ -673,17 +687,20 @@ static unsigned int mt8183_calculate_factor(int clock) > static const struct mtk_dpi_conf mt8173_conf = { > .cal_factor = mt8173_calculate_factor, > .reg_h_fre_con = 0xe0, > + .max_clock_khz = 300000, > }; > > static const struct mtk_dpi_conf mt2701_conf = { > .cal_factor = mt2701_calculate_factor, > .reg_h_fre_con = 0xb0, > .edge_sel_en = true, > + .max_clock_khz = 150000, > }; > > static const struct mtk_dpi_conf mt8183_conf = { > .cal_factor = mt8183_calculate_factor, > .reg_h_fre_con = 0xe0, > + .max_clock_khz = 100000, > }; > > static int mtk_dpi_probe(struct platform_device *pdev) > -- > 2.25.1 > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 52f11a63a330..ffa4a0f1989f 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -118,6 +118,7 @@ struct mtk_dpi_yc_limit { struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); u32 reg_h_fre_con; + u32 max_clock_khz; bool edge_sel_en; }; @@ -555,9 +556,22 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) mtk_dpi_set_display_mode(dpi, &dpi->mode); } +static enum drm_mode_status +mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_mode *mode) +{ + struct mtk_dpi *dpi = bridge_to_dpi(bridge); + + if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = { .attach = mtk_dpi_bridge_attach, .mode_set = mtk_dpi_bridge_mode_set, + .mode_valid = mtk_dpi_bridge_mode_valid, .disable = mtk_dpi_bridge_disable, .enable = mtk_dpi_bridge_enable, }; @@ -673,17 +687,20 @@ static unsigned int mt8183_calculate_factor(int clock) static const struct mtk_dpi_conf mt8173_conf = { .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0, + .max_clock_khz = 300000, }; static const struct mtk_dpi_conf mt2701_conf = { .cal_factor = mt2701_calculate_factor, .reg_h_fre_con = 0xb0, .edge_sel_en = true, + .max_clock_khz = 150000, }; static const struct mtk_dpi_conf mt8183_conf = { .cal_factor = mt8183_calculate_factor, .reg_h_fre_con = 0xe0, + .max_clock_khz = 100000, }; static int mtk_dpi_probe(struct platform_device *pdev)
Add per-platform max clock rate check in mtk_dpi_bridge_mode_valid. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)