| Message ID | 20210209101955.8836-1-bharat.kumar.gogada@xilinx.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI | expand |
Hi Bharat, Thank you for sending the patches over! > Add support for routing PCIe DMA traffic coherently when > Cache Coherent Interconnect (CCI) is enabled in the system. > The "dma-coherent" property is used to determine if CCI is enabled > or not. > Refer https://developer.arm.com/documentation/ddi0470/k/preface > for CCI specification. [...] A small nitpick, so feel free to ignore, of course. Perhaps "Refer to" and "for the CCI", etc. [...] > + /* This routes the PCIe DMA traffic to go through CCI path */ > + if (of_dma_is_coherent(dev->of_node)) { > + nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) | > + CFG_PCIE_CACHE, BRCFG_PCIE_RX1); > + } [...] A suggestion. You can drop the curly brackets here if you want to keep the style used in the kernel, especially for when there is a single statement inside the code block. Krzysztof
> Hi Bharat, > > Thank you for sending the patches over! > > > Add support for routing PCIe DMA traffic coherently when Cache > > Coherent Interconnect (CCI) is enabled in the system. > > The "dma-coherent" property is used to determine if CCI is enabled or > > not. > > Refer https://developer.arm.com/documentation/ddi0470/k/preface > > for CCI specification. > [...] > > A small nitpick, so feel free to ignore, of course. > > Perhaps "Refer to" and "for the CCI", etc. > > [...] > > + /* This routes the PCIe DMA traffic to go through CCI path */ > > + if (of_dma_is_coherent(dev->of_node)) { > > + nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, > BRCFG_PCIE_RX1) | > > + CFG_PCIE_CACHE, BRCFG_PCIE_RX1); > > + } > [...] > > A suggestion. > > You can drop the curly brackets here if you want to keep the style used in > the kernel, especially for when there is a single statement inside the code > block. > Thanks Krzysztof. Will remove it.
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 07e36661bbc2..08e060574cb7 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -26,6 +26,7 @@ /* Bridge core config registers */ #define BRCFG_PCIE_RX0 0x00000000 +#define BRCFG_PCIE_RX1 0x00000004 #define BRCFG_INTERRUPT 0x00000010 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020 @@ -128,6 +129,7 @@ #define NWL_ECAM_VALUE_DEFAULT 12 #define CFG_DMA_REG_BAR GENMASK(2, 0) +#define CFG_PCIE_CACHE GENMASK(7, 0) #define INT_PCI_MSI_NR (2 * 32) @@ -675,6 +677,12 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, BRCFG_PCIE_RX_MSG_FILTER); + /* This routes the PCIe DMA traffic to go through CCI path */ + if (of_dma_is_coherent(dev->of_node)) { + nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) | + CFG_PCIE_CACHE, BRCFG_PCIE_RX1); + } + err = nwl_wait_for_link(pcie); if (err) return err;
Add support for routing PCIe DMA traffic coherently when Cache Coherent Interconnect (CCI) is enabled in the system. The "dma-coherent" property is used to determine if CCI is enabled or not. Refer https://developer.arm.com/documentation/ddi0470/k/preface for CCI specification. Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> --- drivers/pci/controller/pcie-xilinx-nwl.c | 8 ++++++++ 1 file changed, 8 insertions(+)