diff mbox series

[v1,18/18] arm64: dts: imx8mq: Add node to G2 hardware

Message ID 20210217080306.157876-19-benjamin.gaignard@collabora.com (mailing list archive)
State New, archived
Headers show
Series Add HANTRO G2/HEVC decoder support for IMX8MQ | expand

Commit Message

Benjamin Gaignard Feb. 17, 2021, 8:03 a.m. UTC 
Split VPU node in two: one for G1 and one for G2 since they are
different hardware blocks.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 43 +++++++++++++++++------
 1 file changed, 33 insertions(+), 10 deletions(-)

Comments

Ezequiel Garcia Feb. 17, 2021, 8:43 p.m. UTC | #1 
On Wed, 2021-02-17 at 09:03 +0100, Benjamin Gaignard wrote:
> Split VPU node in two: one for G1 and one for G2 since they are
> different hardware blocks.
> 
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 43 +++++++++++++++++------
>  1 file changed, 33 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index d9d9efc8592d..3cab3f0b9131 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -1287,17 +1287,16 @@ vpu_reset: vpu-reset@38320000 {
>                         #reset-cells = <1>;
>                 };
>  
> -               vpu: video-codec@38300000 {
> +               vpu_g1: video-codec@38300000 {
>                         compatible = "nxp,imx8mq-vpu";
> -                       reg = <0x38300000 0x10000>,
> -                             <0x38310000 0x10000>;
> -                       reg-names = "g1", "g2";
> -                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> -                                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> -                       interrupt-names = "g1", "g2";
> +                       reg = <0x38300000 0x10000>;
> +                       reg-names = "g1";
> +                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "g1";
>                         clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> -                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
> -                       clock-names = "g1", "g2";
> +                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> +                                <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
> +                       clock-names = "g1", "g2", "bus";

How come the G1 block needs the G2 clock?

>                         assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
>                                           <&clk IMX8MQ_CLK_VPU_G2>,
>                                           <&clk IMX8MQ_CLK_VPU_BUS>,
> @@ -1306,12 +1305,36 @@ vpu: video-codec@38300000 {
>                                                  <&clk IMX8MQ_VPU_PLL_OUT>,
>                                                  <&clk IMX8MQ_SYS1_PLL_800M>,
>                                                  <&clk IMX8MQ_VPU_PLL>;
> -                       assigned-clock-rates = <600000000>, <600000000>,
> +                       assigned-clock-rates = <600000000>, <300000000>,
>                                                <800000000>, <0>;
>                         resets = <&vpu_reset IMX8MQ_RESET_VPU_RESET_G1>;
>                         power-domains = <&pgc_vpu>;
>                 };
>  
> +               vpu_g2: video-codec@38310000 {
> +                       compatible = "nxp,imx8mq-vpu-g2";
> +                       reg = <0x38310000 0x10000>;
> +                       reg-names = "g2";
> +                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "g2";
> +                       clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
> +                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>,

Ditto, the G2 block needs the G1 clock?

Thanks,
Ezequiel
Benjamin Gaignard Feb. 18, 2021, 3:47 p.m. UTC | #2 
Le 17/02/2021 à 21:43, Ezequiel Garcia a écrit :
> On Wed, 2021-02-17 at 09:03 +0100, Benjamin Gaignard wrote:
>> Split VPU node in two: one for G1 and one for G2 since they are
>> different hardware blocks.
>>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
>> ---
>>   arch/arm64/boot/dts/freescale/imx8mq.dtsi | 43 +++++++++++++++++------
>>   1 file changed, 33 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> index d9d9efc8592d..3cab3f0b9131 100644
>> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> @@ -1287,17 +1287,16 @@ vpu_reset: vpu-reset@38320000 {
>>                          #reset-cells = <1>;
>>                  };
>>   
>> -               vpu: video-codec@38300000 {
>> +               vpu_g1: video-codec@38300000 {
>>                          compatible = "nxp,imx8mq-vpu";
>> -                       reg = <0x38300000 0x10000>,
>> -                             <0x38310000 0x10000>;
>> -                       reg-names = "g1", "g2";
>> -                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
>> -                                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
>> -                       interrupt-names = "g1", "g2";
>> +                       reg = <0x38300000 0x10000>;
>> +                       reg-names = "g1";
>> +                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> +                       interrupt-names = "g1";
>>                          clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
>> -                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
>> -                       clock-names = "g1", "g2";
>> +                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
>> +                                <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
>> +                       clock-names = "g1", "g2", "bus";
> How come the G1 block needs the G2 clock?

It doesn't, I will remove it in v2

>
>>                          assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
>>                                            <&clk IMX8MQ_CLK_VPU_G2>,
>>                                            <&clk IMX8MQ_CLK_VPU_BUS>,
>> @@ -1306,12 +1305,36 @@ vpu: video-codec@38300000 {
>>                                                   <&clk IMX8MQ_VPU_PLL_OUT>,
>>                                                   <&clk IMX8MQ_SYS1_PLL_800M>,
>>                                                   <&clk IMX8MQ_VPU_PLL>;
>> -                       assigned-clock-rates = <600000000>, <600000000>,
>> +                       assigned-clock-rates = <600000000>, <300000000>,
>>                                                 <800000000>, <0>;
>>                          resets = <&vpu_reset IMX8MQ_RESET_VPU_RESET_G1>;
>>                          power-domains = <&pgc_vpu>;
>>                  };
>>   
>> +               vpu_g2: video-codec@38310000 {
>> +                       compatible = "nxp,imx8mq-vpu-g2";
>> +                       reg = <0x38310000 0x10000>;
>> +                       reg-names = "g2";
>> +                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
>> +                       interrupt-names = "g2";
>> +                       clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
>> +                                <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
> Ditto, the G2 block needs the G1 clock?
>
> Thanks,
> Ezequiel
>
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index d9d9efc8592d..3cab3f0b9131 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1287,17 +1287,16 @@  vpu_reset: vpu-reset@38320000 {
 			#reset-cells = <1>;
 		};
 
-		vpu: video-codec@38300000 {
+		vpu_g1: video-codec@38300000 {
 			compatible = "nxp,imx8mq-vpu";
-			reg = <0x38300000 0x10000>,
-			      <0x38310000 0x10000>;
-			reg-names = "g1", "g2";
-			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "g1", "g2";
+			reg = <0x38300000 0x10000>;
+			reg-names = "g1";
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "g1";
 			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
-				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
-			clock-names = "g1", "g2";
+				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
+				 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+			clock-names = "g1", "g2", "bus";
 			assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
 					  <&clk IMX8MQ_CLK_VPU_G2>,
 					  <&clk IMX8MQ_CLK_VPU_BUS>,
@@ -1306,12 +1305,36 @@  vpu: video-codec@38300000 {
 						 <&clk IMX8MQ_VPU_PLL_OUT>,
 						 <&clk IMX8MQ_SYS1_PLL_800M>,
 						 <&clk IMX8MQ_VPU_PLL>;
-			assigned-clock-rates = <600000000>, <600000000>,
+			assigned-clock-rates = <600000000>, <300000000>,
 					       <800000000>, <0>;
 			resets = <&vpu_reset IMX8MQ_RESET_VPU_RESET_G1>;
 			power-domains = <&pgc_vpu>;
 		};
 
+		vpu_g2: video-codec@38310000 {
+			compatible = "nxp,imx8mq-vpu-g2";
+			reg = <0x38310000 0x10000>;
+			reg-names = "g2";
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "g2";
+			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
+				 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+			clock-names = "g1", "g2", "bus";
+			assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
+					  <&clk IMX8MQ_CLK_VPU_G2>,
+					  <&clk IMX8MQ_CLK_VPU_BUS>,
+					  <&clk IMX8MQ_VPU_PLL_BYPASS>;
+			assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
+						 <&clk IMX8MQ_VPU_PLL_OUT>,
+						 <&clk IMX8MQ_SYS1_PLL_800M>,
+						 <&clk IMX8MQ_VPU_PLL>;
+			assigned-clock-rates = <600000000>, <300000000>,
+					       <800000000>, <0>;
+			resets = <&vpu_reset IMX8MQ_RESET_VPU_RESET_G2>;
+			power-domains = <&pgc_vpu>;
+		};
+
 		pcie0: pcie@33800000 {
 			compatible = "fsl,imx8mq-pcie";
 			reg = <0x33800000 0x400000>,