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[09/13] arm64: dts: qcom: Add reserved memory for fw

Message ID 1613114930-1661-10-git-send-email-rnayak@codeaurora.org (mailing list archive)
State Superseded
Headers show
Series Add binding updates and DT files for SC7280 SoC | expand

Commit Message

Rajendra Nayak Feb. 12, 2021, 7:28 a.m. UTC 
From: Maulik Shah <mkshah@codeaurora.org>

Add fw reserved memory area for CPUCP and AOP.

Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Stephen Boyd Feb. 23, 2021, 7:45 a.m. UTC | #1 
Quoting Rajendra Nayak (2021-02-11 23:28:46)
> From: Maulik Shah <mkshah@codeaurora.org>
> 
> Add fw reserved memory area for CPUCP and AOP.

Does CPUCP stand for CPU Content Protection? AOP is Always On Processor.
It would help if the commit text told us what these acronyms were.

> 
> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
Rajendra Nayak Feb. 23, 2021, 11:45 a.m. UTC | #2 
On 2/23/2021 1:15 PM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2021-02-11 23:28:46)
>> From: Maulik Shah <mkshah@codeaurora.org>
>>
>> Add fw reserved memory area for CPUCP and AOP.
> 
> Does CPUCP stand for CPU Content Protection? AOP is Always On Processor.
> It would help if the commit text told us what these acronyms were.

Thanks, I'll expand the acronyms when I re-post.
  
>>
>> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> ---
>>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++++++++++
>>   1 file changed, 10 insertions(+)
>>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index f71ba21..b5b9b6a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -73,11 +73,21 @@ 
 		#size-cells = <2>;
 		ranges;
 
+		aop_mem: memory@80800000 {
+			reg = <0x0 0x80800000 0x0 0x60000>;
+			no-map;
+		};
+
 		aop_cmd_db_mem: memory@80860000 {
 			reg = <0x0 0x80860000 0x0 0x20000>;
 			compatible = "qcom,cmd-db";
 			no-map;
 		};
+
+		cpucp_mem: memory@80b00000 {
+			no-map;
+			reg = <0x0 0x80b00000 0x0 0x100000>;
+		};
 	};
 
 	cpus {