| Message ID | 1614145010-36079-3-git-send-email-cang@codeaurora.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | None | expand |
> > From: Nitin Rawat <nitirawa@codeaurora.org> > > Disable interrupt in reset path to flush pending IRQ handler in order to > avoid possible NoC issues. > > Signed-off-by: Nitin Rawat <nitirawa@codeaurora.org> > Signed-off-by: Can Guo <cang@codeaurora.org> > --- > drivers/scsi/ufs/ufs-qcom.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c > index f97d7b0..a9dc8d7 100644 > --- a/drivers/scsi/ufs/ufs-qcom.c > +++ b/drivers/scsi/ufs/ufs-qcom.c > @@ -253,12 +253,17 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) > { > int ret = 0; > struct ufs_qcom_host *host = ufshcd_get_variant(hba); > + bool reenable_intr = false; > > if (!host->core_reset) { > dev_warn(hba->dev, "%s: reset control not set\n", __func__); > goto out; > } > > + reenable_intr = hba->is_irq_enabled; > + disable_irq(hba->irq); > + hba->is_irq_enabled = false; > + > ret = reset_control_assert(host->core_reset); > if (ret) { > dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", > @@ -280,6 +285,11 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) > > usleep_range(1000, 1100); > > + if (reenable_intr) { > + enable_irq(hba->irq); > + hba->is_irq_enabled = true; > + } > + If in the future, you will enable UFSHCI_QUIRK_BROKEN_HCE on your platform (currently only for Exynos), Will this code still work?
On 2021-02-28 22:23, Avri Altman wrote: >> >> From: Nitin Rawat <nitirawa@codeaurora.org> >> >> Disable interrupt in reset path to flush pending IRQ handler in order >> to >> avoid possible NoC issues. >> >> Signed-off-by: Nitin Rawat <nitirawa@codeaurora.org> >> Signed-off-by: Can Guo <cang@codeaurora.org> >> --- >> drivers/scsi/ufs/ufs-qcom.c | 10 ++++++++++ >> 1 file changed, 10 insertions(+) >> >> diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c >> index f97d7b0..a9dc8d7 100644 >> --- a/drivers/scsi/ufs/ufs-qcom.c >> +++ b/drivers/scsi/ufs/ufs-qcom.c >> @@ -253,12 +253,17 @@ static int ufs_qcom_host_reset(struct ufs_hba >> *hba) >> { >> int ret = 0; >> struct ufs_qcom_host *host = ufshcd_get_variant(hba); >> + bool reenable_intr = false; >> >> if (!host->core_reset) { >> dev_warn(hba->dev, "%s: reset control not set\n", >> __func__); >> goto out; >> } >> >> + reenable_intr = hba->is_irq_enabled; >> + disable_irq(hba->irq); >> + hba->is_irq_enabled = false; >> + >> ret = reset_control_assert(host->core_reset); >> if (ret) { >> dev_err(hba->dev, "%s: core_reset assert failed, err = >> %d\n", >> @@ -280,6 +285,11 @@ static int ufs_qcom_host_reset(struct ufs_hba >> *hba) >> >> usleep_range(1000, 1100); >> >> + if (reenable_intr) { >> + enable_irq(hba->irq); >> + hba->is_irq_enabled = true; >> + } >> + > If in the future, you will enable UFSHCI_QUIRK_BROKEN_HCE on your > platform (currently only for Exynos), > Will this code still work? Yes, it still works. Thanks, Can Guo.
> > On 2021-02-28 22:23, Avri Altman wrote: > >> > >> From: Nitin Rawat <nitirawa@codeaurora.org> > >> > >> Disable interrupt in reset path to flush pending IRQ handler in order > >> to > >> avoid possible NoC issues. > >> > >> Signed-off-by: Nitin Rawat <nitirawa@codeaurora.org> > >> Signed-off-by: Can Guo <cang@codeaurora.org> Reviewed-by: Avri Altman <avri.altman@wdc.com> > >> --- > >> drivers/scsi/ufs/ufs-qcom.c | 10 ++++++++++ > >> 1 file changed, 10 insertions(+) > >> > >> diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c > >> index f97d7b0..a9dc8d7 100644 > >> --- a/drivers/scsi/ufs/ufs-qcom.c > >> +++ b/drivers/scsi/ufs/ufs-qcom.c > >> @@ -253,12 +253,17 @@ static int ufs_qcom_host_reset(struct ufs_hba > >> *hba) > >> { > >> int ret = 0; > >> struct ufs_qcom_host *host = ufshcd_get_variant(hba); > >> + bool reenable_intr = false; > >> > >> if (!host->core_reset) { > >> dev_warn(hba->dev, "%s: reset control not set\n", > >> __func__); > >> goto out; > >> } > >> > >> + reenable_intr = hba->is_irq_enabled; > >> + disable_irq(hba->irq); > >> + hba->is_irq_enabled = false; > >> + > >> ret = reset_control_assert(host->core_reset); > >> if (ret) { > >> dev_err(hba->dev, "%s: core_reset assert failed, err = > >> %d\n", > >> @@ -280,6 +285,11 @@ static int ufs_qcom_host_reset(struct ufs_hba > >> *hba) > >> > >> usleep_range(1000, 1100); > >> > >> + if (reenable_intr) { > >> + enable_irq(hba->irq); > >> + hba->is_irq_enabled = true; > >> + } > >> + > > If in the future, you will enable UFSHCI_QUIRK_BROKEN_HCE on your > > platform (currently only for Exynos), > > Will this code still work? > > Yes, it still works. > > Thanks, > Can Guo.
diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c index f97d7b0..a9dc8d7 100644 --- a/drivers/scsi/ufs/ufs-qcom.c +++ b/drivers/scsi/ufs/ufs-qcom.c @@ -253,12 +253,17 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) { int ret = 0; struct ufs_qcom_host *host = ufshcd_get_variant(hba); + bool reenable_intr = false; if (!host->core_reset) { dev_warn(hba->dev, "%s: reset control not set\n", __func__); goto out; } + reenable_intr = hba->is_irq_enabled; + disable_irq(hba->irq); + hba->is_irq_enabled = false; + ret = reset_control_assert(host->core_reset); if (ret) { dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", @@ -280,6 +285,11 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) usleep_range(1000, 1100); + if (reenable_intr) { + enable_irq(hba->irq); + hba->is_irq_enabled = true; + } + out: return ret; }