| Message ID | 20210219142523.3464540-18-andrew@aj.id.au (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ipmi: Allow raw access to KCS devices | expand |
On Sat, Feb 20, 2021 at 12:55:21AM +1030, Andrew Jeffery wrote: > Allocating IO and IRQ resources to LPC devices is in-theory an operation > for the host, however ASPEED don't appear to expose this capability > outside the BMC (e.g. SuperIO). Instead, we are left with BMC-internal > registers for managing these resources, so introduce a devicetree > property for KCS devices to describe SerIRQ properties. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > --- > .../bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml > index 1c1cc4265948..808475a2c2ca 100644 > --- a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml > +++ b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml > @@ -47,6 +47,18 @@ properties: > channels the status address is derived from the data address, but the > status address may be optionally provided. > > + aspeed,lpc-interrupts: > + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" > + minItems: 1 > + maxItems: 1 > + description: | > + A 2-cell property expressing the LPC SerIRQ number and the interrupt > + level/sense encoding (specified in the standard fashion). That would be uint32-array with 'maxItems: 2'. > + > + Note that the generated interrupt is issued from the BMC to the host, and > + thus the target interrupt controller is not captured by the BMC's > + devicetree. > + > kcs_chan: > deprecated: true > $ref: '/schemas/types.yaml#/definitions/uint32' > @@ -84,9 +96,11 @@ allOf: > > examples: > - | > + #include <dt-bindings/interrupt-controller/irq.h> > kcs3: kcs@24 { > compatible = "aspeed,ast2600-kcs-bmc"; > reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; > aspeed,lpc-io-reg = <0xca2>; > + aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; > interrupts = <8>; > }; > -- > 2.27.0 >
On Sat, 6 Mar 2021, at 09:39, Rob Herring wrote: > On Sat, Feb 20, 2021 at 12:55:21AM +1030, Andrew Jeffery wrote: > > Allocating IO and IRQ resources to LPC devices is in-theory an operation > > for the host, however ASPEED don't appear to expose this capability > > outside the BMC (e.g. SuperIO). Instead, we are left with BMC-internal > > registers for managing these resources, so introduce a devicetree > > property for KCS devices to describe SerIRQ properties. > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > --- > > .../bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml | 14 ++++++++++++++ > > 1 file changed, 14 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml > > index 1c1cc4265948..808475a2c2ca 100644 > > --- a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml > > +++ b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml > > @@ -47,6 +47,18 @@ properties: > > channels the status address is derived from the data address, but the > > status address may be optionally provided. > > > > + aspeed,lpc-interrupts: > > + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" > > + minItems: 1 > > + maxItems: 1 > > + description: | > > + A 2-cell property expressing the LPC SerIRQ number and the interrupt > > + level/sense encoding (specified in the standard fashion). > > That would be uint32-array with 'maxItems: 2'. > Ah, thanks.
diff --git a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml index 1c1cc4265948..808475a2c2ca 100644 --- a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml +++ b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml @@ -47,6 +47,18 @@ properties: channels the status address is derived from the data address, but the status address may be optionally provided. + aspeed,lpc-interrupts: + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + minItems: 1 + maxItems: 1 + description: | + A 2-cell property expressing the LPC SerIRQ number and the interrupt + level/sense encoding (specified in the standard fashion). + + Note that the generated interrupt is issued from the BMC to the host, and + thus the target interrupt controller is not captured by the BMC's + devicetree. + kcs_chan: deprecated: true $ref: '/schemas/types.yaml#/definitions/uint32' @@ -84,9 +96,11 @@ allOf: examples: - | + #include <dt-bindings/interrupt-controller/irq.h> kcs3: kcs@24 { compatible = "aspeed,ast2600-kcs-bmc"; reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; aspeed,lpc-io-reg = <0xca2>; + aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; interrupts = <8>; };
Allocating IO and IRQ resources to LPC devices is in-theory an operation for the host, however ASPEED don't appear to expose this capability outside the BMC (e.g. SuperIO). Instead, we are left with BMC-internal registers for managing these resources, so introduce a devicetree property for KCS devices to describe SerIRQ properties. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- .../bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+)